gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (SME_F8F16): New opt
extension.
(SME_F8F32): Likewise.
(SME_MOP4): Likewise.
* doc/invoke.texi: Document new extension flags.
* config/aarch64/aarch64.h (TARGET_SME_F8F16): New target macro.
(TARGET_SME_F8F32): Likewise.
(TARGET_SME_MOP4): Likewise.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
`__ARM_FEATURE_SME_F8F16`, `__ARM_FEATURE_SME_F8F32` and
`__ARM_FEATURE_SME_MOP4` macros when the relevent extension is enabled.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Test that
`__ARM_FEATURE_SME_F8F16`, `__ARM_FEATURE_SME_F8F32`
and `__ARM_FEATURE_SME_MOP4` macros are defined when the relevelant
extension is enabled.
---
gcc/config/aarch64/aarch64-c.cc | 4 ++++
gcc/config/aarch64/aarch64-option-extensions.def | 5 +++++
gcc/config/aarch64/aarch64.h | 6 ++++++
gcc/doc/invoke.texi | 8 ++++++++
gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c | 5 +++++
5 files changed, 28 insertions(+)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index de4444bacb7..062e7643be5 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -296,7 +296,11 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_F16F16),
"__ARM_FEATURE_SME_F16F16", pfile);
aarch64_def_or_undef (TARGET_SME_F64F64, "__ARM_FEATURE_SME_F64F64", pfile);
+ aarch64_def_or_undef (TARGET_SME_F8F16, "__ARM_FEATURE_SME_F8F16", pfile);
+ aarch64_def_or_undef (TARGET_SME_F8F32, "__ARM_FEATURE_SME_F8F32", pfile);
aarch64_def_or_undef (TARGET_SME2, "__ARM_FEATURE_SME2", pfile);
+ aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_MOP4), "__ARM_FEATURE_SME_MOP4",
+ pfile);
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME2p1),
"__ARM_FEATURE_SME2p1", pfile);
aarch64_def_or_undef (TARGET_FAMINMAX, "__ARM_FEATURE_FAMINMAX", pfile);
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def
b/gcc/config/aarch64/aarch64-option-extensions.def
index 083515d890d..53ae1cabe00 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -251,6 +251,8 @@ AARCH64_OPT_EXTENSION("sme2p1", SME2p1, (SME2), (), (),
"sme2p1")
AARCH64_OPT_EXTENSION("sme-b16b16", SME_B16B16, (SME2, SVE_B16B16), (), (),
"smeb16b16")
+AARCH64_OPT_EXTENSION ("sme-f8f16", SME_F8F16, (SME2), (), (), "smef8f16")
+AARCH64_OPT_EXTENSION ("sme-f8f32", SME_F8F32, (SME2), (), (), "smef8f32")
AARCH64_OPT_EXTENSION("sme-f16f16", SME_F16F16, (SME2), (), (), "smef16f16")
AARCH64_OPT_FMV_EXTENSION("mops", MOPS, (), (), (), "mops")
@@ -287,6 +289,9 @@ AARCH64_OPT_EXTENSION("lut", LUT, (SIMD), (), (), "lut")
AARCH64_OPT_EXTENSION ("sme-lutv2", SME_LUTv2, (SME2), (), (), "sme-lutv2")
+AARCH64_OPT_EXTENSION ("sme-mop4", SME_MOP4, (SME2), (), (), "sme-mop4")
+
+
AARCH64_OPT_EXTENSION("cpa", CPA, (), (), (), "")
#undef AARCH64_OPT_FMV_EXTENSION
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 5a1d5a94670..540dfd00190 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -325,6 +325,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
/* The FEAT_SME_F64F64 extension to SME, enabled through +sme-f64f64. */
#define TARGET_SME_F64F64 AARCH64_HAVE_ISA (SME_F64F64)
+#define TARGET_SME_F8F16 AARCH64_HAVE_ISA (SME_F8F16)
+#define TARGET_SME_F8F32 AARCH64_HAVE_ISA (SME_F8F32)
+
/* SME2 instructions, enabled through +sme2. */
#define TARGET_SME2 AARCH64_HAVE_ISA (SME2)
@@ -463,6 +466,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
elements are enabled through +sme-lutv2. */
#define TARGET_SME_LUTv2 AARCH64_HAVE_ISA (SME_LUTv2)
+
+#define TARGET_SME_MOP4 (TARGET_SME2 && AARCH64_HAVE_ISA (SME_MOP4))
+
/* Prefer different predicate registers for the output of a predicated
operation over re-using an existing input predicate. */
#define TARGET_SVE_PRED_CLOBBER (TARGET_SVE \
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8db0aa0ceb7..01d82aa0d64 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -23074,9 +23074,17 @@ Enable the Scalable Matrix Extension 2. This also
enables SME instructions.
@item sme-b16b16
Enable the FEAT_SME_B16B16 extension to SME. This also enables SME2
and SVE_B16B16 instructions.
+@item sme-f8f16
+Enable the FEAT_SME_F8F16 extension to SME. This also enables SME2
+@item sme-f8326
+Enable the FEAT_SME_F8F32 extension to SME. This also enables SME2
+instructions.
@item sme-f16f16
Enable the FEAT_SME_F16F16 extension to SME. This also enables SME2
instructions.
+@item sme-mop4
+Enable the FEAT_SME_MOP4 extension to SME. This also enables SME2
+instructions.
@item sme2p1
Enable the Scalable Matrix Extension version 2.1. This also enables SME2
instructions.
diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
index 3799fb46df1..13c5035829a 100644
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_4.c
@@ -179,6 +179,11 @@
#error Foo
#endif
+#pragma GCC target "+nothing+sve2+sme-mop4"
+#ifndef __ARM_FEATURE_SME_MOP4
+#error "__ARM_FEATURE_SME_MOP4 not defined"
+#endif
+
#pragma GCC target "branch-protection=standard"
#ifndef __ARM_FEATURE_BTI_DEFAULT
#error Foo
--
2.43.0
