If both the source and destination are address (GP) registers, emitting
instructions that invert the MSB of the address register is two bytes
shorter if TARGET_DENSITY is enabled than emitting a NEG.S machine inst-
ruction that uses hardware FP registers with two reloads.
/* example */
float test(float a) {
return -a;
}
;; before
test:
entry sp, 32
wfr f0, a2
neg.s f0, f0
rfr a2, f0
retw.n
;; after
test:
entry sp, 32
movi.n a8, 1
slli a8, a8, 31
addi.n a2, a2, a8
retw.n
By the way, in configurations that do not use hardware FP register, the
RTL expansion pass will emit such insns by default.
gcc/ChangeLog:
* config/xtensa/xtensa.md (negsf2):
Add another insn pattern that is valid when TARGET_DENSITY is
enabled and both the source and destination are address registers.
---
gcc/config/xtensa/xtensa.md | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 7dc941f9571..bb26eaabaf1 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -695,13 +695,15 @@
})
(define_insn "negsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (neg:SF (match_operand:SF 1 "register_operand" "f")))]
+ [(set (match_operand:SF 0 "register_operand")
+ (neg:SF (match_operand:SF 1 "register_operand")))
+ (clobber (match_scratch:SI 2))]
"TARGET_HARD_FLOAT"
- "neg.s\t%0, %1"
- [(set_attr "type" "farith")
- (set_attr "mode" "SF")
- (set_attr "length" "3")])
+ {@ [cons: =0, 1, =2; attrs: type, length]
+ [D, D, &a; arith , 7] movi.n\t%2, 1\;slli\t%2, %2, 31\;addi.n\t%0, %1, %2
+ [f, f, X; farith, 3] neg.s\t%0, %1
+ }
+ [(set_attr "mode" "SF")])
;; Logical instructions.
--
2.39.5
