-(define_expand "avg<v_double_trunc>3_floor" - [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand") - (truncate:<V_DOUBLE_TRUNC> - (ashiftrt:VWEXTI - (plus:VWEXTI - (sign_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand")) - (sign_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))))] +(define_expand "avg<mode>3_floor" + [(match_operand:V_VLSI 0 "register_operand") + (match_operand:V_VLSI 1 "register_operand") + (match_operand:V_VLSI 2 "register_operand")] "TARGET_VECTOR"
Couldn't we keep the RTL in order for other optimizations? I'm not really expecting any but at least we'd still have the opportunity. Or does that interfere with the tests?
Apart from that it LGTM, thanks for digging deeper here. -- Regards Robin
