This was fixed with r15-9329-gf183ae0ae891a471764876eb but
only a RISC-V V testcase was added. So this adds an aarch64
SVE testcase too.
Pushed as obvious after a quick test to make sure it passes.
PR middle-end/116595
gcc/testsuite/ChangeLog:
* g++.target/aarch64/sve/pr116595.C: New test.
Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com>
---
gcc/testsuite/g++.target/aarch64/sve/pr116595.C | 7 +++++++
1 file changed, 7 insertions(+)
create mode 100644 gcc/testsuite/g++.target/aarch64/sve/pr116595.C
diff --git a/gcc/testsuite/g++.target/aarch64/sve/pr116595.C
b/gcc/testsuite/g++.target/aarch64/sve/pr116595.C
new file mode 100644
index 00000000000..49874dd0db0
--- /dev/null
+++ b/gcc/testsuite/g++.target/aarch64/sve/pr116595.C
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+#include <arm_sve.h>
+
+void transpose4x4_ps()
+{
+ svfloat32x4_t _r = svfloat32x4_t();
+}
--
2.43.0
