Hi all,
This patch will mention recent changes for Intel x86_64 in GCC 14 and 15.
Ok for wwwdocs?
Thx,
Haochen
---
Mention AVX10.1 option changes, revise AVX10.2 option and mention
APX_F new feature in GCC 15.
---
htdocs/gcc-14/changes.html | 12 ++++++++----
htdocs/gcc-15/changes.html | 33 +++++++++++++++++++++------------
2 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index d720ab87..d8b577b4 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -925,10 +925,14 @@ __asm (".global __flmap_lock" "\n\t"
instruction supports EGPR.
</li>
<li>New ISA extension support for Intel AVX10.1 was added.
- AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or
- <code>-mavx10.1-256</code> compiler switch with 256-bit vector size
- support. 512-bit vector size support for AVX10.1 intrinsics are
- available via the <code>-mavx10.1-512</code> compiler switch.
+ AVX10.1 intrinsics are available via the <code>-mavx10.1-256</code>
+ compiler switch with 256-bit vector size support. 512-bit vector size
+ support for AVX10.1 intrinsics are available via the
+ <code>-mavx10.1-512</code> compiler switch. <code>-mavx10.1</code>
+ enables AVX10.1 intrinsics with 256-bit vector size support in GCC 14.1
+ and GCC 14.2. Since GCC 14.3, it enables AVX10.1 intrinsics with 512-bit
+ vector size support. Since GCC 14.3, using <code>-mavx10.1</code> will
+ emit a warning due to this behavior change.
</li>
<li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
AVX-VNNI-INT16 intrinsics are available via the
<code>-mavxvnniint16</code>
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html
index 42b713a2..4cd7bdee 100644
--- a/htdocs/gcc-15/changes.html
+++ b/htdocs/gcc-15/changes.html
@@ -586,29 +586,29 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
AMX-TRANSPOSE intrinsics are available via the
<code>-mamx-transpose</code>
compiler switch.
</li>
+ <li>All of new feature support for Intel APX expect for CFCMOV was added,
+ including CCMP/CTEST, NF and ZU. APX support is available via the
+ <code>-mapxf</code> compiler switch.
+ </li>
<li>New ISA extension support for Intel AVX10.2 was added.
- AVX10.2 intrinsics are available via the <code>-mavx10.2</code> or
- <code>-mavx10.2-256</code> compiler switch with 256-bit vector size
- support. 512-bit vector size support for AVX10.2 intrinsics are
- available via the <code>-mavx10.2-512</code> compiler switch.
+ AVX10.2 intrinsics are available via the <code>-mavx10.2</code>
+ compiler switch.
</li>
<li>New ISA extension support for Intel MOVRS was added.
MOVRS intrinsics are available via the <code>-mmovrs</code>
- compiler switch. 128- and 256- bit MOVRS intrinsics are available via
- the <code>-mmovrs -mavx10.2</code> compiler switch. 512-bit MOVRS
- intrinsics are available via the <code>-mmovrs -mavx10.2-512</code>
- compiler switch.
+ compiler switch. MOVRS vector intrinsics are available via
+ the <code>-mmovrs -mavx10.2</code> compiler switch.
</li>
<li>EVEX version support for Intel SM4 was added.
New 512-bit SM4 intrinsics are available via the
- <code>-msm4 -mavx10.2-512</code> compiler switch.
+ <code>-msm4 -mavx10.2</code> compiler switch.
</li>
<li>GCC now supports the Intel CPU named Diamond Rapids through
<code>-march=diamondrapids</code>.
Based on Granite Rapids, the switch further enables the AMX-AVX512,
- AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2 with 512-bit
- support, AVX-IFMA. AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8,
- CMPccXADD, MOVRS, SHA512, SM3, SM4 and USER_MSR ISA extensions.
+ AMX-FP8, AMX-MOVRS, AMX-TF32, AMX-TRANSPOSE, APX_F, AVX10.2, AVX-IFMA,
+ AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, MOVRS, SHA512,
+ SM3, SM4 and USER_MSR ISA extensions.
</li>
<li>Support for Xeon Phi CPUs (a.k.a. Knight Landing and Knight Mill) were
removed in GCC 15. GCC will no longer accept <code>-march=knl</code>,
@@ -617,6 +617,15 @@ asm (".text; %cc0: mov %cc2, %%r0; .previous;"
<code>-mavx512pf</code>, <code>-mprefetchwt1</code>,
<code>-mtune=knl</code>, and <code>-mtune=knm</code> compiler switches.
</li>
+ <li><code>-mavx10.1-256</code>, <code>-mavx10.1-512</code> and
+ <code>-mevex512</code> are marked as deprecated. Meanwhile,
+ <code>-mavx10.1</code> enables AVX10.1 intrinsics with 512-bit
+ vector size support, while in GCC 14.1 and GCC 14.2, it only enables
+ 256-bit vector size support. GCC will emit a warning when using these
+ compiler switches. <code>-mavx10.1-256</code>, <code>-mavx10.1-512</code>
+ and <code>-mevex512</code> will be removed in GCC 16, while the warning
+ for the behavior change on <code>-mavx10.1</code> will also be removed.
+ </li>
<li>With the <code>-mveclibabi</code> compiler switch GCC is able to generate
vectorized calls to external libraries. GCC 15 newly supports generating
vectorized math calls to the math library from AMD Optimizing CPU Libraries
--
2.31.1
