While looking at enabling vld1x?.c and vst1x?.c tests on arm, I
noticed several inconsistencies in testcases under advsimd-intrinsics
and related effective-targets.
1- The dg-do-what action is computed by advsimd-intrinsics.exp
depending on the actual target, so there normally should be no
'dg-do' directive except if we want to make sure we never try to
run or compile a given testcase.
2- Similarly, advsimd-intrinsics.exp makes use of the torture
framework, so we should not use dg-options.
3- When an effective target tries to detect which flags to use to
enable an architectural feature, the current first option "" does
not work when the testsuite is executed with overridden flags
(e.g. forcing an M-profile target). It has to use -mfpu=auto to
achieve the intended effect.
4- Such effective targets also use -mcpu=unset which is not supported
on aarch64, resulting in many testcases being UNSUPPORTED when they
used to PASS.
Patch 1 is obvious, it fixes a probable typo.
Patches 2-5 address points 1 and 2 above.
Patches 6 and 8-10 address points 3 and 4.
Patch 7 actually enables vld1x?.c and vst1x.c tests on arm.
The series globally extends testing coverage, especially on aarch64
where many tests had inadvertently become unsupported.
Christophe Lyon (10):
testsuite: arm: remove duplicate -mcpu=unset in arm_v8_1_lob_ok
testsuite: aarch64: arm: move saturating_arithmetic_autovect tests to
simd/
testsuite: aarch64: restore torture options in bf16_dup.c
testsuite: aarch64: restore torture options in
vml[as]_float_not_used.c
testsuite: aarch64: arm: Remove redundant dg-do run in
advsimd-intrinsics tests
testsuite: aarch64: arm: Add -mfpu=auto to arm_v8_2a_bf16_neon_ok
testsuite: aarch64: arm: Enable vld1x?.c and vst1x?.c on arm [PR71233]
testsuite: aarch64: arm: Fix -mcpu=unset support in some effective
targets
testsuite: aarch64: arm: Fix -mfpu=auto support in fp16_neon_ok
testsuite: aarch64: arm: Fix -mcpu=unset -mfpu=auto support in more
effective targets
.../aarch64/advsimd-intrinsics/bf16_dup.c | 2 +-
.../aarch64/advsimd-intrinsics/vabdh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vabsh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vaddh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcageh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcagth_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcaleh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcalth_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vceqh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vceqzh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcgeh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcgezh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcgth_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcgtzh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcleh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vclezh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vclth_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vcltzh_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtah_s16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtah_s32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtah_s64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtah_u16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtah_u32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtah_u64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_f16_s16_1.c | 1 -
.../advsimd-intrinsics/vcvth_f16_s32_1.c | 1 -
.../advsimd-intrinsics/vcvth_f16_s64_1.c | 1 -
.../advsimd-intrinsics/vcvth_f16_u16_1.c | 1 -
.../advsimd-intrinsics/vcvth_f16_u32_1.c | 1 -
.../advsimd-intrinsics/vcvth_f16_u64_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_f16_s16_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_f16_s32_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_f16_s64_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_f16_u16_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_f16_u32_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_f16_u64_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_s16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_s32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_s64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_u16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_u32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_n_u64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_s16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_s32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_s64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_u16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_u32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvth_u64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtmh_s16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtmh_s32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtmh_s64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtmh_u16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtmh_u32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtmh_u64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtnh_s16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtnh_s32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtnh_s64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtnh_u16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtnh_u32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtnh_u64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtph_s16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtph_s32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtph_s64_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtph_u16_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtph_u32_f16_1.c | 1 -
.../advsimd-intrinsics/vcvtph_u64_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vdiv_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vdivh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vduph_lane.c | 1 -
.../aarch64/advsimd-intrinsics/vfmah_f16_1.c | 1 -
.../advsimd-intrinsics/vfmas_lane_f16_1.c | 1 -
.../advsimd-intrinsics/vfmas_n_f16_1.c | 1 -
.../advsimd-intrinsics/vfmash_lane_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vfmsh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vld1x2.c | 23 ++--
.../aarch64/advsimd-intrinsics/vld1x3.c | 23 ++--
.../aarch64/advsimd-intrinsics/vld1x4.c | 25 ++--
.../aarch64/advsimd-intrinsics/vmaxh_f16_1.c | 1 -
.../advsimd-intrinsics/vmaxnmh_f16_1.c | 1 -
.../advsimd-intrinsics/vmaxnmv_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vmaxv_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vminh_f16_1.c | 1 -
.../advsimd-intrinsics/vminnmh_f16_1.c | 1 -
.../advsimd-intrinsics/vminnmv_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vminv_f16_1.c | 1 -
.../advsimd-intrinsics/vmla_float_not_fused.c | 2 -
.../advsimd-intrinsics/vmls_float_not_fused.c | 2 -
.../advsimd-intrinsics/vmul_lane_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vmulh_f16_1.c | 1 -
.../advsimd-intrinsics/vmulh_lane_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vmulx_f16_1.c | 1 -
.../advsimd-intrinsics/vmulx_lane_f16_1.c | 1 -
.../advsimd-intrinsics/vmulx_n_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vmulxh_f16_1.c | 1 -
.../advsimd-intrinsics/vmulxh_lane_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vnegh_f16_1.c | 1 -
.../advsimd-intrinsics/vpminmaxnm_f16_1.c | 1 -
.../advsimd-intrinsics/vqrshrn_high_n.c | 1 -
.../advsimd-intrinsics/vqrshrun_high_n.c | 1 -
.../advsimd-intrinsics/vqshrn_high_n.c | 1 -
.../advsimd-intrinsics/vqshrun_high_n.c | 1 -
.../advsimd-intrinsics/vrecpeh_f16_1.c | 1 -
.../advsimd-intrinsics/vrecpsh_f16_1.c | 1 -
.../advsimd-intrinsics/vrecpxh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndah_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndi_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndih_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndmh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndnh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndph_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vrndxh_f16_1.c | 1 -
.../advsimd-intrinsics/vrsqrteh_f16_1.c | 1 -
.../advsimd-intrinsics/vrsqrtsh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vsqrt_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vsqrth_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vst1x2.c | 23 ++--
.../aarch64/advsimd-intrinsics/vst1x3.c | 23 ++--
.../aarch64/advsimd-intrinsics/vst1x4.c | 25 ++--
.../aarch64/advsimd-intrinsics/vsubh_f16_1.c | 1 -
.../aarch64/advsimd-intrinsics/vtrn_half.c | 1 -
.../aarch64/advsimd-intrinsics/vuzp_half.c | 1 -
.../aarch64/advsimd-intrinsics/vzip_half.c | 1 -
.../saturating_arithmetic_autovect.inc | 0
.../saturating_arithmetic_autovect_1.c | 0
.../saturating_arithmetic_autovect_2.c | 0
.../saturating_arithmetic_autovect_3.c | 0
.../saturating_arithmetic_autovect_4.c | 0
gcc/testsuite/lib/target-supports.exp | 127 ++++++++++++++----
129 files changed, 191 insertions(+), 198 deletions(-)
rename gcc/testsuite/gcc.target/aarch64/{advsimd-intrinsics =>
simd}/saturating_arithmetic_autovect.inc (100%)
rename gcc/testsuite/gcc.target/aarch64/{advsimd-intrinsics =>
simd}/saturating_arithmetic_autovect_1.c (100%)
rename gcc/testsuite/gcc.target/aarch64/{advsimd-intrinsics =>
simd}/saturating_arithmetic_autovect_2.c (100%)
rename gcc/testsuite/gcc.target/aarch64/{advsimd-intrinsics =>
simd}/saturating_arithmetic_autovect_3.c (100%)
rename gcc/testsuite/gcc.target/aarch64/{advsimd-intrinsics =>
simd}/saturating_arithmetic_autovect_4.c (100%)
--
2.34.1
