From: Robert Suchanek <robert.sucha...@mips.com> Add peepholes to remove silly moves. These reloads happens because of different modes making elimination non-trivial.
Cherry-picked 85462a9dbf8d659bfb0417d354a0a4f9cd4b8e07 from https://github.com/MIPS/gcc Signed-off-by: Robert Suchanek <robert.sucha...@imgtec.com> Signed-off-by: Faraz Shahbazker <fshahbaz...@wavecomp.com> Signed-off-by: Aleksandar Rakic <aleksandar.ra...@htecgroup.com> --- gcc/config/mips/mips.md | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 159fc2e2615..1243f20f344 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -5254,6 +5254,18 @@ [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") (set_attr "mode" "HI")]) +(define_peephole2 + [(set (match_operand:HI 0 "register_operand") + (match_operand:HI 1 "register_operand")) + (set (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "register_operand"))] + "TARGET_MIPS16 + && REGNO (operands[1]) == REGNO (operands[2]) + && REGNO (operands[0]) == REGNO (operands[3]) + && peep2_reg_dead_p (2, operands[3])" + [(const_int 0)] + "") + ;; On the mips16, we can split lh $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. @@ -5330,6 +5342,18 @@ [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo") (set_attr "mode" "QI")]) +(define_peephole2 + [(set (match_operand:QI 0 "register_operand") + (match_operand:QI 1 "register_operand")) + (set (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "register_operand"))] + "TARGET_MIPS16 + && REGNO (operands[1]) == REGNO (operands[2]) + && REGNO (operands[0]) == REGNO (operands[3]) + && peep2_reg_dead_p (2, operands[3])" + [(const_int 0)] + "") + ;; On the mips16, we can split lb $r,N($r) into an add and a load, ;; when the original load is a 4 byte instruction but the add and the ;; load are 2 2 byte instructions. -- 2.34.1
