Re: [PATCH 3/4] RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extension

[Robin Dapp]

I'm going to push the attached as obvious if my local test shows
no issues.

Regards
 Robin

[PATCH] RISC-V: Unbreak bootstrap.

This fixes a wrong format specifier and an unused variable which should
re-enable bootstrap.

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_file_end): Fix format string.
        (riscv_lshift_subword): Mark MODE as unused.
---
 gcc/config/riscv/riscv.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f5e672bb7f5..5a3a0504177 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10375,7 +10375,7 @@ riscv_file_end ()
       fprintf (asm_out_file, "\t.long\t4f - 3f\n");
       fprintf (asm_out_file, "3:\n");
       /* zicfiss, zicfilp.  */
-      fprintf (asm_out_file, "\t.long\t%x\n", feature_1_and);
+      fprintf (asm_out_file, "\t.long\t%lx\n", feature_1_and);
       fprintf (asm_out_file, "4:\n");
       fprintf (asm_out_file, "\t.p2align\t%u\n", p2align);
       fprintf (asm_out_file, "5:\n");
@@ -11959,7 +11959,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx 
*shift, rtx *mask,
 /* Leftshift a subword within an SImode register.  */
 
 void
-riscv_lshift_subword (machine_mode mode, rtx value, rtx shift,
+riscv_lshift_subword (machine_mode mode ATTRIBUTE_UNUSED, rtx value, rtx shift,
                      rtx *shifted_value)
 {
   rtx value_reg = gen_reg_rtx (SImode);
-- 
2.47.1