Saurabh Jha <saurabh....@arm.com> writes:
> On 1/8/2025 11:13 AM, Richard Sandiford wrote:
>> <saurabh....@arm.com> writes:
>>> [...]
>>> diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
>>> b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
>>> index e726fa1fb68..0c4f8251ac0 100644
>>> --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
>>> +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def
>>> @@ -164,6 +164,10 @@ DEF_SVE_FUNCTION (svwhilegt, compare_scalar, while,
>>> none)
>>> DEF_SVE_FUNCTION (svwhilerw, compare_ptr, all_data, none)
>>> DEF_SVE_FUNCTION (svwhilewr, compare_ptr, all_data, none)
>>> DEF_SVE_FUNCTION (svxar, ternary_shift_right_imm, all_integer, none)
>>> +DEF_SVE_FUNCTION (svluti2_lane, luti2, bhs_data, none)
>>> +DEF_SVE_FUNCTION (svluti4_lane, luti4, bhs_data, none)
>>> +DEF_SVE_FUNCTION_GS (svluti4_lane, luti4, bhs_data, x2, none)
>>
>> bhs_data looks wrong: there should be no .s versions. Similarly...
>>
>>> +
>>> #undef REQUIRED_EXTENSIONS
>>>
>>> #define REQUIRED_EXTENSIONS nonstreaming_sve (AARCH64_FL_SVE2)
>>> [...]
>>> diff --git a/gcc/config/aarch64/aarch64-sve2.md
>>> b/gcc/config/aarch64/aarch64-sve2.md
>>> index f8cfe08f4c0..7dcbc0700da 100644
>>> --- a/gcc/config/aarch64/aarch64-sve2.md
>>> +++ b/gcc/config/aarch64/aarch64-sve2.md
>>> @@ -133,6 +133,7 @@
>>> ;; ---- Optional AES extensions
>>> ;; ---- Optional SHA-3 extensions
>>> ;; ---- Optional SM4 extensions
>>> +;; ---- Table lookup
>>>
>>> ;;
>>> =========================================================================
>>> ;; == Moves
>>> @@ -4211,3 +4212,47 @@
>>> "sm4ekey\t%0.s, %1.s, %2.s"
>>> [(set_attr "type" "crypto_sm4")]
>>> )
>>> +
>>> +;;
>>> -------------------------------------------------------------------------
>>> +;; ---- Table lookup
>>> +;;
>>> -------------------------------------------------------------------------
>>> +;; Includes:
>>> +;; - LUTI2
>>> +;; - LUTI4
>>> +;;
>>> -------------------------------------------------------------------------
>>> +
>>> +(define_insn "@aarch64_sve_luti<LUTI_BITS><mode>"
>>> + [(set (match_operand:SVE_FULL_BS 0 "register_operand" "=w")
>>> + (unspec:SVE_FULL_BS
>>> + [(match_operand:SVE_FULL_BS 1 "register_operand" "w")
>>> + (match_operand:VNx16QI 2 "register_operand" "w")
>>> + (match_operand:DI 3 "const_int_operand")
>>> + (const_int LUTI_BITS)]
>>> + UNSPEC_SVE_LUTI))]
>>> + "TARGET_SVE2"
>>> + "luti<LUTI_BITS>\t%0.<Vetype>, { %1.<Vetype> }, %2[%3]"
>>> +)
>>> +
>>> +(define_insn "@aarch64_sve_luti<LUTI_BITS><mode>"
>>> + [(set (match_operand:<VSINGLE> 0 "register_operand" "=w")
>>> + (unspec:<VSINGLE>
>>> + [(match_operand:SVE_FULL_H 1 "aligned_register_operand" "w")
>>> + (match_operand:VNx16QI 2 "register_operand" "w")
>>> + (match_operand:DI 3 "const_int_operand")
>>> + (const_int LUTI_BITS)]
>>> + UNSPEC_SVE_LUTI))]
>>> + "TARGET_SVE2"
>>> + "luti<LUTI_BITS>\t%0.<Vetype>, { %1.<Vetype> }, %2[%3]"
>>> +)
>>
>> ...there should be .S (VNx4) variants here. Also, the .H variants
>> don't require an aligned register operand. (FWIW, using "w" with
>> "aligned_register_operand" is wrong in any case, since "w" accepts
>> unaligned registers.)
>
> You meant "..x2" here, right?
I did mean VNx4 (the mode prefix for full .S vectors, as in VNx4SI).
But I also meant "there should be *no* .S" -- sorry about that.
Richard
