Some tests add options for V and Zvbb extensions, but those extensions
are not compatible with the E ABI variants. This leads to spurious test
failures when toolchain's default ABI is ILP32E or ILP64E:
spawn ... -march=rv32ecv_zvbb ...
cc1: error: ILP32E ABI does not support the 'D' extension
cc1: sorry, unimplemented: Currently the 'V' implementation requires the 'M'
extension
Fix by skipping the tests when toolchain's default ABI is E variant.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vandn-1.c: Skip if default
is E ABI.
* gcc.target/riscv/rvv/autovec/binop/vrolr-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vwsll-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vwsll-template.h: Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c:
Ditto.
* gcc.target/riscv/rvv/autovec/unop/clz-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/ctz-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/popcount-3.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-3.c: Ditto.
* gcc.target/riscv/rvv/base/cmpmem-4.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-1.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-2.c: Ditto.
* gcc.target/riscv/rvv/base/cpymem-3.c: Ditto.
* gcc.target/riscv/rvv/base/movmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/pr115068.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-1.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-2.c: Ditto.
* gcc.target/riscv/rvv/base/setmem-3.c: Ditto.
* gcc.target/riscv/rvv/base/vwaddsub-1.c: Ditto.
Signed-off-by: Dimitar Dimitrov <dimi...@dinux.eu>
---
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/binop/vwsll-template.h | 2 +-
.../riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c | 2 +-
22 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
index 3bb5bf8dd5b..dfdc64b568d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vandn-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
index 55dac27697c..1c5f6e046d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrolr-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
index a2e5b4f5aa1..0a67db77a6a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
index 376cbaee0d5..89b7624fe9f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vwsll-template.h
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
index 1fd3644886a..de5a5ed7d56 100644
---
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
index c27d9d399b9..483b58f8af7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/clz-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
index d5989bd5aad..2425dc86404 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/ctz-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
index 1396e46ec8c..12324f19867 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
index 116cc304da3..7e6880370e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
index 00b87a07fd8..6bf89099884 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-3.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options "riscv_v" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
index 6bc8b07bc2c..9edd6cb54ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
index 5ca31af90fb..82aa3076579 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
index 5860b27a233..e2dd6a1c45f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 81d14d83633..654c80087d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
index 7b6a429f34c..3d79b5987fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-2.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2
-mrvv-max-lmul=m8" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
index f07078ba6a7..2b75b314fae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-3.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-additional-options "-O1 -fno-schedule-insns -fno-schedule-insns2
-mrvv-max-lmul=m8" } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
index 1f148bc7052..03e633be271 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
index 8359e81629d..af2cba6039d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
index 22844ff348c..a22d366de9b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
index 838fbebadff..a10886862b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
index 44933819715..460a8f2c7fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
index 196215a1f7b..6e027a555f3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddsub-1.c
@@ -1,2 +1,2 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { ! riscv_abi_e } } } */
/* { dg-add-options riscv_v } */
--
2.47.1
