[PATCH V4 4/4] Use vector pair load/store for memcpy with -mcpu=future

[Michael Meissner]

In the development for the power10 processor, GCC did not enable using the load
vector pair and store vector pair instructions when optimizing things like
memory copy.  This patch enables using those instructions if -mcpu=future is
used.

I have built GCC with the patches in this patch set applied on both little and
big endian PowerPC systems and there were no regressions.  Can I apply this
patch to GCC 15?

2024-11-16  Michael Meissner  <meiss...@linux.ibm.com>

gcc/

        * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using
        load vector pair and store vector pair instructions for memory copy
        operations.
        (POWERPC_MASKS): Make the bit for enabling using load vector pair and
        store vector pair operations set and reset when the PowerPC processor is
        changed.
        * gcc/config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable
        -mblock-ops-vector-pair from influcing .machine selection.

gcc/testsuite/

        * gcc.target/powerpc/future-3.c: New test.
---
 gcc/config/rs6000/rs6000-cpus.def           |  4 +++-
 gcc/config/rs6000/rs6000.cc                 |  2 +-
 gcc/testsuite/gcc.target/powerpc/future-3.c | 21 +++++++++++++++++++++
 3 files changed, 25 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/future-3.c

diff --git a/gcc/config/rs6000/rs6000-cpus.def 
b/gcc/config/rs6000/rs6000-cpus.def
index e2e7c5ff191..62e6c9d3b58 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -90,7 +90,8 @@
                              | OPTION_MASK_POWER11)
 
 #define FUTURE_MASKS_SERVER    (POWER11_MASKS_SERVER                   \
-                                | OPTION_MASK_FUTURE)
+                                | OPTION_MASK_FUTURE                   \
+                                | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR)
 
 /* Flags that need to be turned off if -mno-vsx.  */
 #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX    \
@@ -120,6 +121,7 @@
 
 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
 #define POWERPC_MASKS          (OPTION_MASK_ALTIVEC                    \
+                                | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR    \
                                 | OPTION_MASK_CMPB                     \
                                 | OPTION_MASK_CRYPTO                   \
                                 | OPTION_MASK_DFP                      \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 19086c59afe..183940f07bd 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5907,7 +5907,7 @@ rs6000_machine_from_flags (void)
 
   /* Disable the flags that should never influence the .machine selection.  */
   flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
-            | OPTION_MASK_ALTIVEC);
+            | OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR);
 
   if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
     return "future";
diff --git a/gcc/testsuite/gcc.target/powerpc/future-3.c 
b/gcc/testsuite/gcc.target/powerpc/future-3.c
new file mode 100644
index 00000000000..1cbe9170f12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/future-3.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test to see that memcpy will use load/store vector pair with
+   -mcpu=future.  */
+
+#ifndef SIZE
+#define SIZE 4
+#endif
+
+extern vector double to[SIZE], from[SIZE];
+
+void
+copy (void)
+{
+  __builtin_memcpy (to, from, sizeof (to));
+  return;
+}
+
+/* { dg-final { scan-assembler {\mlxvpx?\M}  } } */
+/* { dg-final { scan-assembler {\mstxvpx?\M} } } */
-- 
2.47.0


-- 
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com