Peter Bergner asked me to reorganize my V3 patch that separates the architecture bits (set via -mcpu=<xxx>) compared to the ISA bits that are based on options.
Here is the beginning of the V3 patch for reference: https://gcc.gnu.org/pipermail/gcc-patches/2024-November/668643.html As Peter has suggested, I reworked the patch so the the bits where I rename the target flags comes before the bit about separating the architecture bits. I also moved the -mcpu=future bits before the architecture bits as well. There are 4 separate patch sets (that might have separate patches within the patch sets). Each of the patch sets is a logical entity. The 4 patch sets are: 1: Rename the TARGET_<xxx> options so that they say TARGET_POWER5 instead of TARGET_POPCNTB. In this patch set, TARGET_POWER5 is a macro that references TARGET_POPCNTB. The 5 patches in this patch set rename each option in turn. 2: Add support for -mcpu=future. Because the architecture mask support is in the 4th patch set, this patch set adds a dummy switch -mfuture. 3: Make -mvsx not internally set -mcpu=power7. This has come up in several bugs. This is independent of the other patches, and can be omitted if desired. 4: The last patch set now provides the separation between the architecture bits and the ISA bits. It removes several of the dummy switches (-mpower10, -mpower11, -mfuture) that were added to support those processors, but users aren't supposed to use those options. This is the second patch set that adds -mcpu=future. Because this patch set is being offered before the separation between the architecture and ISA bits, we have to add an internal undocumented switch (-mfuture) that will be later removed if patch set #4 is approved. This patch is written assuming the 5 patches from the first patch set have been applied to GCC 15. That patch set is at: https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669067.html There are 4 patches in this series: 1: The first patch adds all of the support for -mcpu=future except for modifying power10.md. 2: The second patch modifies power10.md so that -mtune=future acts the same as -mtune=power11 or -mtune=power10. 3: The third patch adds two tests to make sure -mcpu=future and __attribute__((target("cpu=future"))) both work. 4: The fourth patch allows GCC to generate load/store vector pair instructions for doing memory operations. Originally we had planned to use these instruction for power10 when they were introduced. However, we needed to disable using these instructions by default for performance reasons. It is hoped that potentional future machines will fix the underlying performance issue and we can use load/store vector pair instructions. I have built GCC with these patches applied on both little and big endian PowerPC systems and there were no regressions. Can I apply these patches to GCC 15? -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: meiss...@linux.ibm.com
