On 10/20/24 1:40 PM, Vineet Gupta wrote:
This inhibits sched1 aggressive spilling on RISC-V (see prev commit for
details of what the hook does).
On RISC-V (BPI-F3) we see good results.
(Build: -Ofast -march=rv64gcv_zba_zbb_zbs)
Before:
------
Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par':
4,769,844.10 msec task-clock:u # 1.000 CPUs
utilized
6,029 context-switches:u # 1.264 /sec
0 cpu-migrations:u # 0.000 /sec
201,468 page-faults:u # 42.238 /sec
7,631,707,552,979 cycles:u # 1.600 GHz
2,630,225,489,010 instructions:u # 0.34 insn per
cycle
10,592,305,077 branches:u # 2.221 M/sec
16,274,388 branch-misses:u # 0.15% of all
branches
After:
-----
Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par':
4,471,770.20 msec task-clock:u # 0.998 CPUs
utilized
159,245 context-switches:u # 35.611 /sec
2 cpu-migrations:u # 0.000 /sec
204,065 page-faults:u # 45.634 /sec
7,153,778,156,281 cycles:u ( 6% faster) # 1.600 GHz
2,143,115,846,207 instructions:u (18.5% fewer) # 0.30 insn per
cycle
10,592,316,035 branches:u # 2.369 M/sec
17,229,411 branch-misses:u # 0.16% of all
branches
Similarly, good results on Cactu on aarch64 as well (qemu dynamic icounts only)
(Build: -march=armv9-a+sve2)
Before: 1,382,403,783,566
After: 1,264,869,192,921 (8.5% improv)
gcc/ChangeLog:
PR target/114729
* config/riscv/riscv.cc (TARGET_SCHED_PRESSURE_PREFER_NARROW):
Define to true.
gcc/testsuite/ChangeLog:
PR target/114729
* gcc.target/riscv/riscv.exp: Enable new tests to build.
* gcc.target/riscv/sched1-spills/spill1.cpp: Add new test.
This is fine once we finalize naming for patch #1 and update this patch
for whatever final name is selected.
I worry ever-so-slightly about the testcase being overly-sensitive to
unrelated changes, but not overly so. If it turns out to require
regular twiddling, then we'll deal with it at that time.
jeff
