On 8/13/24 3:19 AM, Richard Sandiford wrote:
And the inconsistency was driving me bananas as my mental model is that
(reg:DI N) covers N and N+1 and all that changes in the order based on
endianness. ie, if we have (set (reg:DI 0) (...)) that changes d0/d1.
But maybe that's just 20 years of little endian thinking creeping in.
In which case (subreg:DI (reg:SI d0) 0) is actually meaningless.
Yeah. The same problem can happen for little-endian too, with e.g.
a doubleword paradoxical subreg of the final hard register leaking
into the virtual registers. But the failure mode tends to be less
brutal then. That case is probably more like big-endian
(subreg:DI (reg:SI a0) 0), where the combination d7+a0 would be
rejected for register class reasons.
I think the only sensible move is to revert, re-open the bz and
re-analyze. Damn. Back into reload ;(
jeff
