This patch adds support for RISC-V RVA23 and RVB23 Profiles[1], which depend on the base RISC-V Profiles support[2].
[1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New Profiles. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-22.c: New test. * gcc.target/riscv/attribute-23.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 20 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++++++++++ gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++++++++++ 3 files changed, 41 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 23ae07fe2f3..e6e8adf5e1b 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -323,6 +323,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, @@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] = "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" "_zicboz_zfhmin_zkt"}, + /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension + 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + + + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + /* Currently we do not define S/M mode Profiles in gcc part. */ /* Terminate the list. */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c b/gcc/testsuite/gcc.target/riscv/attribute-22.c new file mode 100644 index 00000000000..0bbb3242ddd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=RVA23U64 -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" +_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" +_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c b/gcc/testsuite/gcc.target/riscv/attribute-23.c new file mode 100644 index 00000000000..459b5641ca3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=RVB23U64 -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0" +"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0" +"_zbb1p0_zbs1p0_zkt1p0\"" } } */ -- 2.25.1
