> On 25 Jul 2024, at 04:14, Andrew Pinski <quic_apin...@quicinc.com> wrote: > > External email: Use caution opening links or attachments > > > Now there is an optab for bic, andn since r15-1890-gf379596e0ba99d. > This moves aarch64_bic for sve over to use it instead. > > Note unlike the simd bic patterns, the operands were already > in the order that was expected for the optab so no swapping > was needed. > > Built and tested on aarch64-linux-gnu with no regressions.
Looks ok to me but please give Richard S a day or two in case I’ve missed something. Thanks, Kyrill > > gcc/ChangeLog: > > * config/aarch64/aarch64-sve-builtins-base.cc (svbic_impl::expand): > Update > to use andn optab instead of using code_for_aarch64_bic. > * config/aarch64/aarch64-sve.md (@aarch64_bic<mode>): Rename to ... > (andn<mode>3): This. > > Signed-off-by: Andrew Pinski <quic_apin...@quicinc.com> > --- > gcc/config/aarch64/aarch64-sve-builtins-base.cc | 2 +- > gcc/config/aarch64/aarch64-sve.md | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc > b/gcc/config/aarch64/aarch64-sve-builtins-base.cc > index aa26370d397..a2268353ae3 100644 > --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc > +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc > @@ -271,7 +271,7 @@ public: > } > > if (e.pred == PRED_x) > - return e.use_unpred_insn (code_for_aarch64_bic (e.vector_mode (0))); > + return e.use_unpred_insn (e.direct_optab_handler (andn_optab)); > > return e.use_cond_insn (code_for_cond_bic (e.vector_mode (0))); > } > diff --git a/gcc/config/aarch64/aarch64-sve.md > b/gcc/config/aarch64/aarch64-sve.md > index 5331e7121d5..c3ed5075c4e 100644 > --- a/gcc/config/aarch64/aarch64-sve.md > +++ b/gcc/config/aarch64/aarch64-sve.md > @@ -4641,8 +4641,8 @@ (define_insn "<optab><mode>3" > ;; - BIC > ;; ------------------------------------------------------------------------- > > -;; Unpredicated BIC. > -(define_expand "@aarch64_bic<mode>" > +;; Unpredicated BIC; andn named pattern. > +(define_expand "andn<mode>3" > [(set (match_operand:SVE_I 0 "register_operand") > (and:SVE_I > (unspec:SVE_I > -- > 2.43.0 >
