[PATCH 1/5] RISC-V: Small stack tie changes

[Raphael Moreira Zinsly]

Enable the register used by riscv_emit_stack_tie () to be passed as
an argument so we can tie the stack with other registers besides
hard_frame_pointer_rtx.
Also don't allow operand 1 of stack_tie<mode> to be optimized to sp
in preparation for the stack clash protection support.

gcc/ChangeLog:
        * config/riscv/riscv.cc (riscv_emit_stack_tie): Pass the
          register to be tied to the stack pointer as argument.
        * config/riscv/riscv.md (stack_tie<mode>): Don't match equal
          operands.
---
 gcc/config/riscv/riscv.cc | 18 +++++++++---------
 gcc/config/riscv/riscv.md |  2 +-
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 19b9b2daa95..f85d018c514 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7891,12 +7891,12 @@ riscv_adjust_multi_push_cfi_prologue (int saved_size)
 }
 
 static void
-riscv_emit_stack_tie (void)
+riscv_emit_stack_tie (rtx reg)
 {
   if (Pmode == SImode)
-    emit_insn (gen_stack_tiesi (stack_pointer_rtx, hard_frame_pointer_rtx));
+    emit_insn (gen_stack_tiesi (stack_pointer_rtx, reg));
   else
-    emit_insn (gen_stack_tiedi (stack_pointer_rtx, hard_frame_pointer_rtx));
+    emit_insn (gen_stack_tiedi (stack_pointer_rtx, reg));
 }
 
 /*zcmp multi push and pop code_for_push_pop function ptr array  */
@@ -8077,7 +8077,7 @@ riscv_expand_prologue (void)
                            GEN_INT ((frame->hard_frame_pointer_offset - 
remaining_size).to_constant ()));
       RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
 
-      riscv_emit_stack_tie ();
+      riscv_emit_stack_tie (hard_frame_pointer_rtx);
     }
 
   /* Save the V registers.  */
@@ -8108,7 +8108,7 @@ riscv_expand_prologue (void)
             allocation is ordered WRT fp setup and subsequent writes
             into the frame.  */
          if (frame_pointer_needed)
-           riscv_emit_stack_tie ();
+           riscv_emit_stack_tie (hard_frame_pointer_rtx);
          return;
        }
 
@@ -8147,7 +8147,7 @@ riscv_expand_prologue (void)
         allocation is ordered WRT fp setup and subsequent writes
         into the frame.  */
       if (frame_pointer_needed)
-       riscv_emit_stack_tie ();
+       riscv_emit_stack_tie (hard_frame_pointer_rtx);
     }
 }
 
@@ -8282,7 +8282,7 @@ riscv_expand_epilogue (int style)
   if (cfun->calls_alloca)
     {
       /* Emit a barrier to prevent loads from a deallocated stack.  */
-      riscv_emit_stack_tie ();
+      riscv_emit_stack_tie (hard_frame_pointer_rtx);
       need_barrier_p = false;
 
       poly_int64 adjust_offset = -frame->hard_frame_pointer_offset;
@@ -8376,7 +8376,7 @@ riscv_expand_epilogue (int style)
   if (known_gt (step1, 0))
     {
       /* Emit a barrier to prevent loads from a deallocated stack.  */
-      riscv_emit_stack_tie ();
+      riscv_emit_stack_tie (hard_frame_pointer_rtx);
       need_barrier_p = false;
 
       /* Restore the scalable frame which is assigned in prologue.  */
@@ -8476,7 +8476,7 @@ riscv_expand_epilogue (int style)
     frame->mask = mask; /* Undo the above fib.  */
 
   if (need_barrier_p)
-    riscv_emit_stack_tie ();
+    riscv_emit_stack_tie (hard_frame_pointer_rtx);
 
   /* Deallocate the final bit of the frame.  */
   if (step2.to_constant () > 0)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 46c46039c33..5780c5abacf 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3969,7 +3969,7 @@
        (unspec:BLK [(match_operand:X 0 "register_operand" "r")
                     (match_operand:X 1 "register_operand" "r")]
                    UNSPEC_TIE))]
-  ""
+  "!rtx_equal_p (operands[0], operands[1])"
   ""
   [(set_attr "type" "ghost")
    (set_attr "length" "0")]
-- 
2.42.0