[PATCH v2] RISC-V: xtheadmemidx: Fix mode test for pre/post-modify addressing

[Christoph Müllner]

auto_inc_dec (-O3) performs optimizations like the following
if RVV and XTheadMemIdx is enabled.

(insn 23 20 27 3 (set (mem:V4QI (reg:DI 136 [ ivtmp.13 ]) [0 MEM <vector(4) 
char> [(char *)_39]+0 S4 A32])
        (reg:V4QI 168)) "gcc/testsuite/gcc.target/riscv/pr116033.c":12:27 3183 
{*movv4qi}
     (nil))
(insn 40 39 41 3 (set (reg:DI 136 [ ivtmp.13 ])
        (plus:DI (reg:DI 136 [ ivtmp.13 ])
            (const_int 20 [0x14]))) 5 {adddi3}
     (nil))
====>
(insn 23 20 27 3 (set (mem:V4QI (post_modify:DI (reg:DI 136 [ ivtmp.13 ])
                (plus:DI (reg:DI 136 [ ivtmp.13 ])
                    (const_int 20 [0x14]))) [0 MEM <vector(4) char> [(char 
*)_39]+0 S4 A32])
        (reg:V4QI 168)) "gcc/testsuite/gcc.target/riscv/pr116033.c":12:27 3183 
{*movv4qi}
     (expr_list:REG_INC (reg:DI 136 [ ivtmp.13 ])
        (nil)))

The reason why the pass believes that this is legal is,
that the mode test in th_memidx_classify_address_modify()
requires INTEGRAL_MODE_P (mode), which includes vector modes.

Let's restrict the mode test such, that only MODE_INT is allowed.

        PR target/116033

gcc/ChangeLog:

        * config/riscv/thead.cc (th_memidx_classify_address_modify):
        Fix mode test.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/pr116033.c: New test.

Reported-by: Patrick O'Neill <patr...@rivosinc.com>
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
---
 gcc/config/riscv/thead.cc                 |  6 ++----
 gcc/testsuite/gcc.target/riscv/pr116033.c | 16 ++++++++++++++++
 2 files changed, 18 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr116033.c

diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 951b60888596..6f5edeb7e0ac 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -453,10 +453,8 @@ th_memidx_classify_address_modify (struct 
riscv_address_info *info, rtx x,
   if (!TARGET_XTHEADMEMIDX)
     return false;
 
-  if (!TARGET_64BIT && mode == DImode)
-    return false;
-
-  if (!(INTEGRAL_MODE_P (mode) && GET_MODE_SIZE (mode).to_constant () <= 8))
+  if (GET_MODE_CLASS (mode) != MODE_INT
+      || GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
     return false;
 
   if (GET_CODE (x) != POST_MODIFY
diff --git a/gcc/testsuite/gcc.target/riscv/pr116033.c 
b/gcc/testsuite/gcc.target/riscv/pr116033.c
new file mode 100644
index 000000000000..881922da0260
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr116033.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gv_xtheadmemidx" { target { rv64 } } } */
+/* { dg-options "-march=rv32gv_xtheadmemidx" { target { rv32 } } } */
+
+char arr_3[20][20];
+void init()
+{
+  for (int i_0 = 0; i_0 < 20; ++i_0)
+    for (int i_1 = 0; i_0 < 20; ++i_0)
+      for (int i_1 = 0; i_1 < 20; ++i_0)
+        for (int i_1 = 0; i_1 < 20; ++i_1)
+          arr_3[i_0][i_1] = i_1;
+}
+
+/* { dg-final { scan-assembler-not 
"vse8.v\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),\[0-9\]+,\[0-9\]+" } } */
-- 
2.45.2