On 22/07/2024 11:07, Alex Coplan wrote:
> Hi Claudio,
>
> I've left a couple of small comments below.
>
> On 22/07/2024 09:30, Claudio Bantaloukas wrote:
------8<-----
>>
>> @@ -1505,6 +1513,8 @@ (define_insn_and_split "*movdi_aarch64"
>> [w, w ; fmov , fp , 4] fmov\t%d0, %d1
>> [w, Dd ; neon_move, simd, 4] <<
>> aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);
>> [w, Dx ; neon_move, simd, 8] #
>> + [Umv, r; mrs , * , 8] msr\t%0, %x1
>> + [r, Umv; mrs , * , 8] mrs\t%x0, %1
>
> I think in the case of this pattern (but not the others) the %x modifier
> isn't needed since a DImode operand satisfying "r" should get printed as
> an x register by default.
Some sleep and coffee helped! After re-reading gccint 17.5 Output
Templates and Operand Substitution, I managed to find that
asm_fprintf (f, "%s", reg_names [REGNO (x)]);
is used for registers in aarch64_print_operand. Thank you for the heads up!
Claudio
>
> Thanks,
> Alex
>
>> }
>> "CONST_INT_P (operands[1])
>> && REG_P (operands[0])
>> diff --git a/gcc/config/aarch64/constraints.md
>> b/gcc/config/aarch64/constraints.md
>> index a2569cea510..0c81fb28f7e 100644
>> --- a/gcc/config/aarch64/constraints.md
>> +++ b/gcc/config/aarch64/constraints.md
>> @@ -77,6 +77,9 @@ (define_register_constraint "Upl" "PR_LO_REGS"
>> (define_register_constraint "Uph" "PR_HI_REGS"
>> "SVE predicate registers p8 - p15.")
>>
>> +(define_register_constraint "Umv" "MOVEABLE_SYSREGS"
>> + "@internal System Registers suitable for moving rather than requiring an
>> unspec msr")
>> +
>> (define_constraint "c"
>> "@internal The condition code register."
>> (match_operand 0 "cc_register"))
>> diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
>> b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
>> index b774f28c9f0..10fd128d8f9 100644
>> --- a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
>> +++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
>> @@ -1,14 +1,14 @@
>> /* Test the fp8 ACLE intrinsics family. */
>> /* { dg-do compile } */
>> /* { dg-options "-O1 -march=armv8-a" } */
>> -/* { dg-final { check-function-bodies "**" "" } } */
>> +/* { dg-final { check-function-bodies "**" "" "" } } */
>>
>> #ifdef __ARM_FEATURE_FP8
>> #error "__ARM_FEATURE_FP8 feature macro defined."
>> #endif
>>
>> #pragma GCC push_options
>> -#pragma GCC target ("arch=armv9.4-a+fp8")
>> +#pragma GCC target("arch=armv9.4-a+fp8")
>>
>> #include <arm_acle.h>
>>
>> @@ -16,4 +16,105 @@
>> #error "__ARM_FEATURE_FP8 feature macro not defined."
>> #endif
>>
>> -#pragma GCC pop_options
>> +/*
>> +**test_write_fpmr_sysreg_asm_64:
>> +** msr fpmr, x0
>> +** ret
>> +*/
>> +void
>> +test_write_fpmr_sysreg_asm_64 (uint64_t val)
>> +{
>> + register uint64_t fpmr asm ("fpmr") = val;
>> + asm volatile ("" ::"Umv"(fpmr));
>> +}
>> +
>> +/*
>> +**test_write_fpmr_sysreg_asm_32:
>> +** uxtw x0, w0
>> +** msr fpmr, x0
>> +** ret
>> +*/
>> +void
>> +test_write_fpmr_sysreg_asm_32 (uint32_t val)
>> +{
>> + register uint64_t fpmr asm ("fpmr") = val;
>> + asm volatile ("" ::"Umv"(fpmr));
>> +}
>> +
>> +/*
>> +**test_write_fpmr_sysreg_asm_16:
>> +** and x0, x0, 65535
>> +** msr fpmr, x0
>> +** ret
>> +*/
>> +void
>> +test_write_fpmr_sysreg_asm_16 (uint16_t val)
>> +{
>> + register uint64_t fpmr asm ("fpmr") = val;
>> + asm volatile ("" ::"Umv"(fpmr));
>> +}
>> +
>> +/*
>> +**test_write_fpmr_sysreg_asm_8:
>> +** and x0, x0, 255
>> +** msr fpmr, x0
>> +** ret
>> +*/
>> +void
>> +test_write_fpmr_sysreg_asm_8 (uint8_t val)
>> +{
>> + register uint64_t fpmr asm ("fpmr") = val;
>> + asm volatile ("" ::"Umv"(fpmr));
>> +}
>> +
>> +/*
>> +**test_read_fpmr_sysreg_asm_64:
>> +** mrs x0, fpmr
>> +** ret
>> +*/
>> +uint64_t
>> +test_read_fpmr_sysreg_asm_64 ()
>> +{
>> + register uint64_t fpmr asm ("fpmr");
>> + asm volatile ("" : "=Umv"(fpmr) :);
>> + return fpmr;
>> +}
>> +
>> +/*
>> +**test_read_fpmr_sysreg_asm_32:
>> +** mrs x0, fpmr
>> +** ret
>> +*/
>> +uint32_t
>> +test_read_fpmr_sysreg_asm_32 ()
>> +{
>> + register uint32_t fpmr asm ("fpmr");
>> + asm volatile ("" : "=Umv"(fpmr) :);
>> + return fpmr;
>> +}
>> +
>> +/*
>> +**test_read_fpmr_sysreg_asm_16:
>> +** mrs x0, fpmr
>> +** ret
>> +*/
>> +uint16_t
>> +test_read_fpmr_sysreg_asm_16 ()
>> +{
>> + register uint16_t fpmr asm ("fpmr");
>> + asm volatile ("" : "=Umv"(fpmr) :);
>> + return fpmr;
>> +}
>> +
>> +/*
>> +**test_read_fpmr_sysreg_asm_8:
>> +** mrs x0, fpmr
>> +** ret
>> +*/
>> +uint8_t
>> +test_read_fpmr_sysreg_asm_8 ()
>> +{
>> + register uint8_t fpmr asm ("fpmr");
>> + asm volatile ("" : "=Umv"(fpmr) :);
>> + return fpmr;
>> +}
>
