This introduces the relevant flags to enable access to the fpmr register and
fp8 intrinsics, which will be added subsequently.
The `+fp8' -march modifier defines the __ARM_FEATURE_FP8 macro to 1.
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (__ARM_FEATURE_FP8): New.
* config/aarch64/aarch64-option-extensions.def (fp8): Likewise.
(the): Likewise.
* config/aarch64/aarch64.h (TARGET_FP8): Likewise.
* doc/invoke.texi (AArch64 Options): Document new -march flags
and extensions.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/fp8.c: New test.
---
gcc/config/aarch64/aarch64-c.cc | 1 +
.../aarch64/aarch64-option-extensions.def | 2 ++
gcc/config/aarch64/aarch64.h | 3 +++
gcc/doc/invoke.texi | 2 ++
gcc/testsuite/gcc.target/aarch64/acle/fp8.c | 19 +++++++++++++++++++
5 files changed, 27 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/fp8.c
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc
index f9b9e379375..592e71d8404 100644
--- a/gcc/config/aarch64/aarch64-c.cc
+++ b/gcc/config/aarch64/aarch64-c.cc
@@ -276,6 +276,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
cpp_undef (pfile, "__FLT_EVAL_METHOD_C99__");
builtin_define_with_int_value ("__FLT_EVAL_METHOD_C99__",
c_flt_eval_method (false));
+ aarch64_def_or_undef (TARGET_FP8, "__ARM_FEATURE_FP8", pfile);
}
/* Implement TARGET_CPU_CPP_BUILTINS. */
diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index 42ec0eec31e..6998627f377 100644
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -232,6 +232,8 @@ AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
+AARCH64_OPT_EXTENSION("fp8", FP8, (SIMD), (), (), "fp8")
+
#undef AARCH64_OPT_FMV_EXTENSION
#undef AARCH64_OPT_EXTENSION
#undef AARCH64_FMV_FEATURE
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 8056c337957..40793aab814 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -462,6 +462,9 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
&& (aarch64_tune_params.extra_tuning_flags \
& AARCH64_EXTRA_TUNE_AVOID_PRED_RMW))
+/* fp8 instructions are enabled through +fp8. */
+#define TARGET_FP8 AARCH64_HAVE_ISA (FP8)
+
/* Standard register usage. */
/* 31 64-bit general purpose registers R0-R30:
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4850c7379bf..46dee3e4521 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21777,6 +21777,8 @@ Enable support for Armv9.4-a Guarded Control Stack extension.
Enable support for Armv8.9-a/9.4-a translation hardening extension.
@item rcpc3
Enable the RCpc3 (Release Consistency) extension.
+@item fp8
+Enable the fp8 (8-bit floating point) extension.
@end table
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/fp8.c b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
new file mode 100644
index 00000000000..b774f28c9f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/fp8.c
@@ -0,0 +1,19 @@
+/* Test the fp8 ACLE intrinsics family. */
+/* { dg-do compile } */
+/* { dg-options "-O1 -march=armv8-a" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#ifdef __ARM_FEATURE_FP8
+#error "__ARM_FEATURE_FP8 feature macro defined."
+#endif
+
+#pragma GCC push_options
+#pragma GCC target ("arch=armv9.4-a+fp8")
+
+#include <arm_acle.h>
+
+#ifndef __ARM_FEATURE_FP8
+#error "__ARM_FEATURE_FP8 feature macro not defined."
+#endif
+
+#pragma GCC pop_options
