From: Pan Li <pan2...@intel.com>
After the middle-end supported the vector mode of .SAT_ADD, add more
testcases to ensure the correctness of RISC-V backend for form 1. Aka:
Form 1:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \
T __attribute__((noinline)) \
vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1; \
}
DEF_VEC_SAT_U_ADD_IMM_FMT_1 (uint64_t, 9)
Passed the fully rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add help
test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: New
test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: New
test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../riscv/rvv/autovec/binop/vec_sat_arith.h | 26 ++
.../riscv/rvv/autovec/binop/vec_sat_data.h | 256 ++++++++++++++++++
.../rvv/autovec/binop/vec_sat_u_add_imm-1.c | 14 +
.../rvv/autovec/binop/vec_sat_u_add_imm-2.c | 14 +
.../rvv/autovec/binop/vec_sat_u_add_imm-3.c | 14 +
.../rvv/autovec/binop/vec_sat_u_add_imm-4.c | 14 +
.../autovec/binop/vec_sat_u_add_imm-run-1.c | 28 ++
.../autovec/binop/vec_sat_u_add_imm-run-2.c | 28 ++
.../autovec/binop/vec_sat_u_add_imm-run-3.c | 28 ++
.../autovec/binop/vec_sat_u_add_imm-run-4.c | 28 ++
10 files changed, 450 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
index a3116033fb3..0e5e07a38b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h
@@ -3,6 +3,15 @@
#include <stdint-gcc.h>
#include <stdbool.h>
+#include <stdio.h>
+
+#define VALIDATE_RESULT(out, expect, N) \
+ do \
+ { \
+ for (unsigned i = 0; i < N; i++) \
+ if (out[i] != expect[i]) __builtin_abort (); \
+ } \
+ while (false)
/******************************************************************************/
/* Saturation Add (unsigned and signed)
*/
@@ -139,6 +148,23 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \
vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N)
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \
+T __attribute__((noinline)) \
+vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ out[i] = (T)(in[i] + IMM) >= in[i] ? (in[i] + IMM) : -1; \
+}
+#define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \
+ DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM)
+
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
+ vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N)
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed)
*/
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h
new file mode 100644
index 00000000000..0146138a3c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h
@@ -0,0 +1,256 @@
+#ifndef HAVE_DEFINE_VEC_SAT_DATA_H
+#define HAVE_DEFINE_VEC_SAT_DATA_H
+
+#define N 16
+#define TEST_UNARY_DATA(T, NAME) test_##T##_##NAME##_data
+#define TEST_UNARY_DATA_WRAP(T, NAME) TEST_UNARY_DATA(T, NAME)
+
+uint8_t TEST_UNARY_DATA(uint8_t, sat_u_add_imm)[][2][N] =
+{
+ { /* For add imm 0 */
+ {
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ },
+ {
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ 0, 1, 5, 255,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ },
+ },
+ { /* For add imm 254 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 254, 255, 254, 255,
+ 254, 255, 254, 255,
+ 254, 255, 254, 255,
+ 254, 255, 254, 255,
+ },
+ },
+ { /* For add imm 255 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 255, 255, 255, 255,
+ 255, 255, 255, 255,
+ 255, 255, 255, 255,
+ 255, 255, 255, 255,
+ },
+ },
+};
+
+uint16_t TEST_UNARY_DATA(uint16_t, sat_u_add_imm)[][2][N] =
+{
+ { /* For add imm 0 */
+ {
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ },
+ {
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ 0, 1, 5, 65535,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ },
+ },
+ { /* For add imm 65534 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 65534, 65535, 65534, 65535,
+ 65534, 65535, 65534, 65535,
+ 65534, 65535, 65534, 65535,
+ 65534, 65535, 65534, 65535,
+ },
+ },
+ { /* For add imm 65535 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ 65535, 65535, 65535, 65535,
+ },
+ },
+};
+
+uint32_t TEST_UNARY_DATA(uint32_t, sat_u_add_imm)[][2][N] =
+{
+ { /* For add imm 0 */
+ {
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ },
+ {
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ 0, 1, 5, 4294967295,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ },
+ },
+ { /* For add imm 4294967294 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 4294967294, 4294967295, 4294967294, 4294967295,
+ 4294967294, 4294967295, 4294967294, 4294967295,
+ 4294967294, 4294967295, 4294967294, 4294967295,
+ 4294967294, 4294967295, 4294967294, 4294967295,
+ },
+ },
+ { /* For add imm 4294967295 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ 4294967295, 4294967295, 4294967295, 4294967295,
+ },
+ },
+};
+
+uint64_t TEST_UNARY_DATA(uint64_t, sat_u_add_imm)[][2][N] =
+{
+ { /* For add imm 0 */
+ {
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ },
+ {
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ 0, 1, 5, 18446744073709551615u,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ 1, 2, 1, 9,
+ },
+ },
+ { /* For add imm 18446744073709551614 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551614u, 18446744073709551615u,
+ 18446744073709551614u, 18446744073709551615u,
+ },
+ },
+ { /* For add imm 18446744073709551615 */
+ {
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ 0, 1, 0, 8,
+ },
+ {
+ 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u,
+ 18446744073709551615u, 18446744073709551615u,
+ },
+ },
+};
+
+#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c
new file mode 100644
index 00000000000..e5350734749
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm9_uint8_t_fmt_1:
+** ...
+** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c
new file mode 100644
index 00000000000..2319f0730a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm15_uint16_t_fmt_1:
+** ...
+** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint16_t, 15)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c
new file mode 100644
index 00000000000..bc5d0ef026a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm33_uint32_t_fmt_1:
+** ...
+** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint32_t, 33)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c
new file mode 100644
index 00000000000..3912dc465c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm129_uint64_t_fmt_1:
+** ...
+** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint64_t, 129)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c
new file mode 100644
index 00000000000..41524753a35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint8_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 0)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 1)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 254)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 255)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 254, N);
+ RUN (T, out, d[3][0], d[3][1], 255, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c
new file mode 100644
index 00000000000..dba87ac0720
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint16_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 0)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 1)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 65534)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 65535)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 65534, N);
+ RUN (T, out, d[3][0], d[3][1], 65535, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c
new file mode 100644
index 00000000000..cf96f14b341
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint32_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 0)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 1)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 4294967295)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 4294967294)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 4294967294, N);
+ RUN (T, out, d[3][0], d[3][1], 4294967295, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c
new file mode 100644
index 00000000000..8ec1f1a40b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint64_t
+#define RUN(T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 0)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 1)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 18446744073709551614u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP (T, 18446744073709551615u)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+ RUN (T, out, d[0][0], d[0][1], 0, N);
+ RUN (T, out, d[1][0], d[1][1], 1, N);
+ RUN (T, out, d[2][0], d[2][1], 18446744073709551614u, N);
+ RUN (T, out, d[3][0], d[3][1], 18446744073709551615u, N);
+
+ return 0;
+}
--
2.34.1
