Committed, thanks Jeff. Pan
-----Original Message----- From: Jeff Law <jeffreya...@gmail.com> Sent: Monday, August 21, 2023 11:06 PM To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang <yanzhang.w...@intel.com>; kito.ch...@gmail.com Subject: Re: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API On 8/17/23 02:05, Pan Li via Gcc-patches wrote: > From: Pan Li <pan2...@intel.com> > > This patch would like to support the rounding mode API for the > VFWREDUSUM.VS as the below samples > > * __riscv_vfwredusum_vs_f32m1_f64m1_rm > * __riscv_vfwredusum_vs_f32m1_f64m1_rm_m > > Signed-off-by: Pan Li <pan2...@intel.com> > > gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-bases.cc > (vfwredusum_frm_obj): New declaration. > (BASE): Ditto. > * config/riscv/riscv-vector-builtins-bases.h: Ditto. > * config/riscv/riscv-vector-builtins-functions.def > (vfwredusum_frm): New intrinsic function def. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/float-point-wredusum.c: New test. OK jeff
