To double confirm, you mean this declaration ? +static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED, HAS_FRM> vfwredusum_frm_obj;
Pan From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Monday, August 21, 2023 2:40 PM To: Li, Pan2 <pan2...@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: Li, Pan2 <pan2...@intel.com>; Wang, Yanzhang <yanzhang.w...@intel.com>; kito.cheng <kito.ch...@gmail.com> Subject: Re: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API Why does this patch not have HAS_FRM? ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2023-08-17 16:05 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; pan2.li<mailto:pan2...@intel.com>; yanzhang.wang<mailto:yanzhang.w...@intel.com>; kito.cheng<mailto:kito.ch...@gmail.com> Subject: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic API From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to support the rounding mode API for the VFWREDUSUM.VS as the below samples * __riscv_vfwredusum_vs_f32m1_f64m1_rm * __riscv_vfwredusum_vs_f32m1_f64m1_rm_m Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (vfwredusum_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwredusum_frm): New intrinsic function def. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-wredusum.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 2 ++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 1 + .../riscv/rvv/base/float-point-wredusum.c | 33 +++++++++++++++++++ 4 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index abf03bab0da..5ee7d3119db 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2548,6 +2548,7 @@ static CONSTEXPR const freducop<UNSPEC_ORDERED, HAS_FRM> vfredosum_frm_obj; static CONSTEXPR const reducop<SMAX> vfredmax_obj; static CONSTEXPR const reducop<SMIN> vfredmin_obj; static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj; +static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED, HAS_FRM> vfwredusum_frm_obj; static CONSTEXPR const widen_freducop<UNSPEC_ORDERED> vfwredosum_obj; static CONSTEXPR const widen_freducop<UNSPEC_ORDERED, HAS_FRM> vfwredosum_frm_obj; static CONSTEXPR const vmv vmv_x_obj; @@ -2810,6 +2811,7 @@ BASE (vfredmin) BASE (vfwredosum) BASE (vfwredosum_frm) BASE (vfwredusum) +BASE (vfwredusum_frm) BASE (vmv_x) BASE (vmv_s) BASE (vfmv_f) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index c1bb164a712..69d4562091f 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -247,6 +247,7 @@ extern const function_base *const vfredmin; extern const function_base *const vfwredosum; extern const function_base *const vfwredosum_frm; extern const function_base *const vfwredusum; +extern const function_base *const vfwredusum_frm; extern const function_base *const vmv_x; extern const function_base *const vmv_s; extern const function_base *const vfmv_f; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index da1157f5a56..3ce06dc60b7 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -508,6 +508,7 @@ DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops) DEF_RVV_FUNCTION (vfwredusum, reduc_alu, no_mu_preds, wf_vs_ops) DEF_RVV_FUNCTION (vfwredosum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops) +DEF_RVV_FUNCTION (vfwredusum_frm, reduc_alu_frm, no_mu_preds, wf_vs_ops) /* 15. Vector Mask Instructions. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c new file mode 100644 index 00000000000..6c888c10c0d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-wredusum.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat64m1_t +test_riscv_vfwredusum_vs_f32m1_f64m1_rm (vfloat32m1_t op1, vfloat64m1_t op2, + size_t vl) { + return __riscv_vfwredusum_vs_f32m1_f64m1_rm (op1, op2, 0, vl); +} + +vfloat64m1_t +test_vfwredusum_vs_f32m1_f64m1_rm_m (vbool32_t mask, vfloat32m1_t op1, + vfloat64m1_t op2, size_t vl) { + return __riscv_vfwredusum_vs_f32m1_f64m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat64m1_t +test_riscv_vfwredusum_vs_f32m1_f64m1 (vfloat32m1_t op1, vfloat64m1_t op2, + size_t vl) { + return __riscv_vfwredusum_vs_f32m1_f64m1 (op1, op2, vl); +} + +vfloat64m1_t +test_vfwredusum_vs_f32m1_f64m1_m (vbool32_t mask, vfloat32m1_t op1, + vfloat64m1_t op2, size_t vl) { + return __riscv_vfwredusum_vs_f32m1_f64m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ -- 2.34.1
