Got you point, thanks kito and will send patch v2 after test. Pan
-----Original Message----- From: Kito Cheng <kito.ch...@gmail.com> Sent: Monday, August 7, 2023 2:35 PM To: Li, Pan2 <pan2...@intel.com> Cc: juzhe.zh...@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, Yanzhang <yanzhang.w...@intel.com> Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic A build-able patch attached, again, it's based on your patch :) On Mon, Aug 7, 2023 at 11:46 AM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > I am not quite sure if I understand it correctly, but I bet below enums are > required by RISC-V mode switching, like FRM_MODE_DYN in entry, or > FRM_MODE_CALL/EXIT in emit. > > > ;; Defines rounding mode of an floating-point operation. > > -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" > > +(define_attr "frm_mode" "" > > (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul") > > - (const_string "dyn")] > > + (const_string "FRM_DYN")] > > (const_string "none"))) > > Pan > > -----Original Message----- > From: Kito Cheng <kito.ch...@gmail.com> > Sent: Monday, August 7, 2023 11:27 AM > To: Li, Pan2 <pan2...@intel.com> > Cc: juzhe.zh...@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang, > Yanzhang <yanzhang.w...@intel.com> > Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding > mode intrinsic > > What about using similar way as vlmul? > > > # NOTE: diff is based on your patch. > [kitoc@hsinchu02 riscv]$ git diff > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h > index 33f7cb1d670..3cb5c23cb09 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -345,6 +345,7 @@ enum floating_point_rounding_mode > FRM_DYN = 7, /* Aka 0b111. */ > FRM_STATIC_MIN = FRM_RNE, > FRM_STATIC_MAX = FRM_RMM, > + FRM_NONE = 8, > }; > > opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode, > diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc > index d5fb8611d6e..3d5dc0c11be 100644 > --- a/gcc/config/riscv/riscv-v.cc > +++ b/gcc/config/riscv/riscv-v.cc > @@ -112,6 +112,7 @@ public: > { > m_has_fp_rounding_mode_p = true; > m_fp_rounding_mode = mode; > + gcc_assert (mode != FRM_NONE); > } > > void add_output_operand (rtx x, machine_mode mode) > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index f966f1ba769..c1a7650fe85 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -865,9 +865,9 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none" > (const_string "none"))) > > ;; Defines rounding mode of an floating-point operation. > -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" > +(define_attr "frm_mode" "" > (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul") > - (const_string "dyn")] > + (const_string "FRM_DYN")] > (const_string "none"))) > > ;; -----------------------------------------------------------------