A build-able patch attached, again, it's based on your patch :)
On Mon, Aug 7, 2023 at 11:46 AM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> I am not quite sure if I understand it correctly, but I bet below enums are
> required by RISC-V mode switching, like FRM_MODE_DYN in entry, or
> FRM_MODE_CALL/EXIT in emit.
>
> > ;; Defines rounding mode of an floating-point operation.
> > -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> > +(define_attr "frm_mode" ""
> > (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
> > - (const_string "dyn")]
> > + (const_string "FRM_DYN")]
> > (const_string "none")))
>
> Pan
>
> -----Original Message-----
> From: Kito Cheng <kito.ch...@gmail.com>
> Sent: Monday, August 7, 2023 11:27 AM
> To: Li, Pan2 <pan2...@intel.com>
> Cc: juzhe.zh...@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>; Wang,
> Yanzhang <yanzhang.w...@intel.com>
> Subject: Re: RE: [PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding
> mode intrinsic
>
> What about using similar way as vlmul?
>
>
> # NOTE: diff is based on your patch.
> [kitoc@hsinchu02 riscv]$ git diff
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 33f7cb1d670..3cb5c23cb09 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -345,6 +345,7 @@ enum floating_point_rounding_mode
> FRM_DYN = 7, /* Aka 0b111. */
> FRM_STATIC_MIN = FRM_RNE,
> FRM_STATIC_MAX = FRM_RMM,
> + FRM_NONE = 8,
> };
>
> opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index d5fb8611d6e..3d5dc0c11be 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -112,6 +112,7 @@ public:
> {
> m_has_fp_rounding_mode_p = true;
> m_fp_rounding_mode = mode;
> + gcc_assert (mode != FRM_NONE);
> }
>
> void add_output_operand (rtx x, machine_mode mode)
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index f966f1ba769..c1a7650fe85 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -865,9 +865,9 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
> (const_string "none")))
>
> ;; Defines rounding mode of an floating-point operation.
> -(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
> +(define_attr "frm_mode" ""
> (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
> - (const_string "dyn")]
> + (const_string "FRM_DYN")]
> (const_string "none")))
>
> ;; -----------------------------------------------------------------
From 29bfcda510cd86f6b4804e0ea2178b2ce8e6671d Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.ch...@sifive.com>
Date: Mon, 7 Aug 2023 14:34:12 +0800
Subject: [PATCH] f
---
gcc/config/riscv/riscv-protos.h | 5 ++-
gcc/config/riscv/riscv-v.cc | 19 ++++----
gcc/config/riscv/riscv.cc | 38 ++++++++--------
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector.md | 80 ++++++++++++++++-----------------
5 files changed, 74 insertions(+), 70 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 33f7cb1d670..395f056f8d2 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -236,7 +236,6 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
tree, unsigned int, tree *);
bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
bool legitimize_move (rtx, rtx);
-int get_frm_mode (rtx);
void emit_vlmax_vsetvl (machine_mode, rtx);
void emit_hard_vlmax_vsetvl (machine_mode, rtx);
void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);
@@ -345,8 +344,12 @@ enum floating_point_rounding_mode
FRM_DYN = 7, /* Aka 0b111. */
FRM_STATIC_MIN = FRM_RNE,
FRM_STATIC_MAX = FRM_RMM,
+ FRM_NONE = 8,
+ FRM_DYN_EXIT = 9,
+ FRM_DYN_CALL = 10,
};
+enum floating_point_rounding_mode get_frm_mode (rtx);
opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
poly_uint64);
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index d5fb8611d6e..9ab6ae17d33 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -112,6 +112,7 @@ public:
{
m_has_fp_rounding_mode_p = true;
m_fp_rounding_mode = mode;
+ gcc_assert (mode <= FRM_DYN);
}
void add_output_operand (rtx x, machine_mode mode)
@@ -1514,8 +1515,8 @@ expand_const_vector (rtx target, rtx src)
}
/* Get the frm mode with given CONST_INT rtx, the default mode is
- FRM_MODE_DYN. */
-int
+ FRM_DYN. */
+enum floating_point_rounding_mode
get_frm_mode (rtx operand)
{
gcc_assert (CONST_INT_P (operand));
@@ -1523,19 +1524,19 @@ get_frm_mode (rtx operand)
switch (INTVAL (operand))
{
case FRM_RNE:
- return FRM_MODE_RNE;
+ return FRM_RNE;
case FRM_RTZ:
- return FRM_MODE_RTZ;
+ return FRM_RTZ;
case FRM_RDN:
- return FRM_MODE_RDN;
+ return FRM_RDN;
case FRM_RUP:
- return FRM_MODE_RUP;
+ return FRM_RUP;
case FRM_RMM:
- return FRM_MODE_RMM;
+ return FRM_RMM;
case FRM_DYN:
- return FRM_MODE_DYN;
+ return FRM_DYN;
default:
- return FRM_MODE_DYN;
+ return FRM_DYN;
}
gcc_unreachable ();
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 75646811019..966aecd4ab4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7811,11 +7811,11 @@ riscv_static_frm_mode_p (int mode)
{
switch (mode)
{
- case FRM_MODE_RDN:
- case FRM_MODE_RUP:
- case FRM_MODE_RTZ:
- case FRM_MODE_RMM:
- case FRM_MODE_RNE:
+ case riscv_vector::FRM_RDN:
+ case riscv_vector::FRM_RUP:
+ case riscv_vector::FRM_RTZ:
+ case riscv_vector::FRM_RMM:
+ case riscv_vector::FRM_RNE:
return true;
default:
return false;
@@ -7831,12 +7831,12 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
{
rtx backup_reg = DYNAMIC_FRM_RTL (cfun);
- if (prev_mode == FRM_MODE_DYN_CALL)
+ if (prev_mode == riscv_vector::FRM_DYN_CALL)
emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL. */
if (mode != prev_mode)
{
- /* TODO: By design, FRM_MODE_xxx used by mode switch which is
+ /* TODO: By design, FRM_xxx used by mode switch which is
different from the FRM value like FRM_RTZ defined in
riscv-protos.h. When mode switching we actually need a conversion
function to convert the mode of mode switching to the actual
@@ -7845,14 +7845,14 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
and then we leverage this assumption when emit. */
rtx frm = gen_int_mode (mode, SImode);
- if (mode == FRM_MODE_DYN_CALL && prev_mode != FRM_MODE_DYN)
+ if (mode == riscv_vector::FRM_DYN_CALL && prev_mode != riscv_vector::FRM_DYN)
/* No need to emit when prev mode is DYN already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN_EXIT && STATIC_FRM_P (cfun)
- && prev_mode != FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
+ && prev_mode != riscv_vector::FRM_DYN && prev_mode != riscv_vector::FRM_DYN_CALL)
/* No need to emit when prev mode is DYN or DYN_CALL already. */
emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
- else if (mode == FRM_MODE_DYN && prev_mode != FRM_MODE_DYN_CALL)
+ else if (mode == riscv_vector::FRM_DYN && prev_mode != riscv_vector::FRM_DYN_CALL)
/* Restore frm value from backup when switch to DYN mode. */
emit_insn (gen_fsrmsi_restore (backup_reg));
else if (riscv_static_frm_mode_p (mode))
@@ -7881,7 +7881,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
}
}
-/* Adjust the FRM_MODE_NONE insn after a call to FRM_MODE_DYN for the
+/* Adjust the FRM_NONE insn after a call to FRM_DYN for the
underlying emit. */
static int
@@ -7890,7 +7890,7 @@ riscv_frm_adjust_mode_after_call (rtx_insn *cur_insn, int mode)
rtx_insn *insn = prev_nonnote_nondebug_insn_bb (cur_insn);
if (insn && CALL_P (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
return mode;
}
@@ -7941,12 +7941,12 @@ riscv_frm_mode_needed (rtx_insn *cur_insn, int code)
if (!insn)
riscv_frm_emit_after_bb_end (cur_insn);
- return FRM_MODE_DYN_CALL;
+ return riscv_vector::FRM_DYN_CALL;
}
- int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : FRM_MODE_NONE;
+ int mode = code >= 0 ? get_attr_frm_mode (cur_insn) : riscv_vector::FRM_NONE;
- if (mode == FRM_MODE_NONE)
+ if (mode == riscv_vector::FRM_NONE)
/* After meet a call, we need to backup the frm because it may be
updated during the call. Here, for each insn, we will check if
the previous insn is a call or not. When previous insn is call,
@@ -8054,7 +8054,7 @@ riscv_frm_mode_after (rtx_insn *insn, int mode)
return mode;
if (frm_unknown_dynamic_p (insn))
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
if (recog_memoized (insn) < 0)
return mode;
@@ -8096,7 +8096,7 @@ riscv_mode_entry (int entity)
/* According to RVV 1.0 spec, all vector floating-point operations use
the dynamic rounding mode in the frm register. Likewise in other
similar places. */
- return FRM_MODE_DYN;
+ return riscv_vector::FRM_DYN;
}
default:
gcc_unreachable ();
@@ -8114,7 +8114,7 @@ riscv_mode_exit (int entity)
case RISCV_VXRM:
return VXRM_MODE_NONE;
case RISCV_FRM:
- return FRM_MODE_DYN_EXIT;
+ return riscv_vector::FRM_DYN_EXIT;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 0a19adc1329..e18a0081297 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1120,6 +1120,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void);
/* Mode switching (Lazy code motion) for RVV rounding mode instructions. */
#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_VECTOR)
-#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, FRM_MODE_NONE}
+#define NUM_MODES_FOR_MODE_SWITCHING {VXRM_MODE_NONE, riscv_vector::FRM_NONE}
#endif /* ! GCC_RISCV_H */
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index f966f1ba769..343dc5a83ae 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -865,10 +865,10 @@ (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
(const_string "none")))
;; Defines rounding mode of an floating-point operation.
-(define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none"
+(define_attr "frm_mode" ""
(cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfdiv,vfwmul")
- (const_string "dyn")]
- (const_string "none")))
+ (symbol_ref "riscv_vector::FRM_DYN")]
+ (symbol_ref "riscv_vector::FRM_NONE")))
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
@@ -6131,7 +6131,7 @@ (define_insn "@pred_<optab><mode>"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6176,7 +6176,7 @@ (define_insn "@pred_<optab><mode>_scalar"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6222,7 +6222,7 @@ (define_insn "@pred_<optab><mode>_scalar"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<optab><mode>_reverse_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6247,7 +6247,7 @@ (define_insn "@pred_<optab><mode>_reverse_scalar"
[(set_attr "type" "<float_insn_type>")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_<copysign><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -6400,7 +6400,7 @@ (define_insn "*pred_<madd_msub><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6435,7 +6435,7 @@ (define_insn "*pred_<macc_msac><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6474,7 +6474,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6533,7 +6533,7 @@ (define_insn "*pred_<madd_msub><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<macc_msac><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6569,7 +6569,7 @@ (define_insn "*pred_<macc_msac><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6608,7 +6608,7 @@ (define_insn_and_rewrite "*pred_mul_<optab><mode>_scalar"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand")
@@ -6672,7 +6672,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6708,7 +6708,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6748,7 +6748,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
(define_expand "@pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand")
@@ -6809,7 +6809,7 @@ (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "*pred_<nmsac_nmacc><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
@@ -6846,7 +6846,7 @@ (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr")
@@ -6886,7 +6886,7 @@ (define_insn_and_rewrite "*pred_mul_neg_<optab><mode>_scalar"
[(set_attr "type" "vfmuladd")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point unary operations
@@ -6924,7 +6924,7 @@ (define_insn "@pred_<optab><mode>"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
(set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<optab><mode>"
[(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
@@ -7020,7 +7020,7 @@ (define_insn "@pred_dual_widen_<optab><mode>"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7047,7 +7047,7 @@ (define_insn "@pred_dual_widen_<optab><mode>_scalar"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_add<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7072,7 +7072,7 @@ (define_insn "@pred_single_widen_add<mode>"
[(set_attr "type" "vfwalu")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_sub<mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7097,7 +7097,7 @@ (define_insn "@pred_single_widen_sub<mode>"
[(set_attr "type" "vfwalu")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
@@ -7123,7 +7123,7 @@ (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated widen floating-point ternary operations
@@ -7158,7 +7158,7 @@ (define_insn "@pred_widen_mul_<optab><mode>"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7187,7 +7187,7 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7216,7 +7216,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7246,7 +7246,7 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7558,7 +7558,7 @@ (define_insn "@pred_fcvt_x<v_su>_f<mode>"
[(set_attr "type" "vfcvtftoi")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_<fix_cvt><mode>"
[(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
@@ -7600,7 +7600,7 @@ (define_insn "@pred_<float_cvt><mode>"
[(set_attr "type" "vfcvtitof")
(set_attr "mode" "<MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point widen conversions
@@ -7630,7 +7630,7 @@ (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_widen_<fix_cvt><mode>"
[(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
@@ -7717,7 +7717,7 @@ (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
[(set_attr "type" "vfncvtftoi")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_narrow_<fix_cvt><mode>"
[(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7759,7 +7759,7 @@ (define_insn "@pred_narrow_<float_cvt><mode>"
[(set_attr "type" "vfncvtitof")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -7782,7 +7782,7 @@ (define_insn "@pred_trunc<mode>"
[(set_attr "type" "vfncvtftof")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
(define_insn "@pred_rod_trunc<mode>"
[(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
@@ -8064,7 +8064,7 @@ (define_insn "@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<VHF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for SF
(define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
@@ -8092,7 +8092,7 @@ (define_insn "@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<VSF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Ordered Reduction Sum for DF
(define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
@@ -8120,7 +8120,7 @@ (define_insn "@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>"
[(set_attr "type" "vfred<order>")
(set_attr "mode" "<VDF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for HF, aka SF = HF op SF
(define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
@@ -8144,7 +8144,7 @@ (define_insn "@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<VHF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; Float Widen Reduction for SF, aka DF = SF * DF
(define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
@@ -8168,7 +8168,7 @@ (define_insn "@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>"
[(set_attr "type" "vfwred<order>")
(set_attr "mode" "<VSF:MODE>")
(set (attr "frm_mode")
- (symbol_ref "(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
;; -------------------------------------------------------------------------------
;; ---- Predicated permutation operations
--
2.40.1
