Committed with the comment update,, thanks Jeff and Juzhe. Pan
-----Original Message----- From: Gcc-patches <gcc-patches-bounces+pan2.li=intel....@gcc.gnu.org> On Behalf Of Jeff Law via Gcc-patches Sent: Thursday, June 15, 2023 3:08 AM To: Lehua Ding <lehua.d...@rivai.ai>; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; rdapp....@gamil.com; jeffreya...@gamil.com; pal...@rivosinc.com Subject: Re: [PATCH V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119] On 6/14/23 05:56, Lehua Ding wrote: > The V2 patch address comments from Juzhe, thanks. > > Hi, > > The reason for this bug is that in the case where the vector register > is set to a fixed length (with > `--param=riscv-autovec-preference=fixed-vlmax` option), > TARGET_PASS_BY_REFERENCE thinks that variables of type vint32m1 can be > passed through two scalar registers, but when GCC calls FUNCTION_VALUE > (call function riscv_get_arg_info inside) it returns NULL_RTX. These > two functions are not unified. The current treatment is to pass all > vector arguments and returns through the function stack, and a new calling > convention for vector registers will be added in the future. > > Best, > Lehua > > PR target/110119 > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for > vector mode > (riscv_pass_by_reference): Return true for vector mode > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/pr110119-1.c: New test. > * gcc.target/riscv/rvv/base/pr110119-2.c: New test. And just to be clear, I've asked for a minor comment update. The usual procedure is to go ahead and post a V3. In this case I'll also give that V3 pre-approval. So no need to wait for additional acks. Post it and it can be committed immediately. jeff
