Factorize vsliq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (mve_insn>): Add vsli.
* config/arm/mve.md (mve_vsliq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vsliq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 2 ++
gcc/config/arm/mve.md | 8 ++++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 3d4a9cf9cc2..7e7219033cf 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -1181,6 +1181,8 @@ (define_int_attr mve_insn [
(VSHRNTQ_N_S "vshrnt") (VSHRNTQ_N_U "vshrnt")
(VSHRQ_M_N_S "vshr") (VSHRQ_M_N_U "vshr")
(VSHRQ_N_S "vshr") (VSHRQ_N_U "vshr")
+ (VSLIQ_M_N_S "vsli") (VSLIQ_M_N_U "vsli")
+ (VSLIQ_N_S "vsli") (VSLIQ_N_U "vsli")
(VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
(VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
(VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index c6f9c0b9afb..a1c2cad9d2e 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -2058,7 +2058,7 @@ (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
;;
;; [vsliq_n_u, vsliq_n_s])
;;
-(define_insn "mve_vsliq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2067,7 +2067,7 @@ (define_insn "mve_vsliq_n_<supf><mode>"
VSLIQ_N))
]
"TARGET_HAVE_MVE"
- "vsli.%#<V_sz_elem>\t%q0, %q2, %3"
+ "<mve_insn>.%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
])
@@ -2960,7 +2960,7 @@ (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
;;
;; [vsliq_m_n_u, vsliq_m_n_s])
;;
-(define_insn "mve_vsliq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2970,7 +2970,7 @@ (define_insn "mve_vsliq_m_n_<supf><mode>"
VSLIQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3"
+ "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
--
2.34.1
