Factorize vrbsrq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New.
(mve_insn): Add vbrsr.
* config/arm/mve.md (mve_vbrsrq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vbrsrq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.
---
gcc/config/arm/iterators.md | 10 ++++++++++
gcc/config/arm/mve.md | 20 ++++++++++----------
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index d1d14488b56..dfc8d9cae72 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -610,6 +610,14 @@ (define_int_iterator MVE_FP_CREATE_ONLY [
VCREATEQ_F
])
+(define_int_iterator MVE_VBRSR_M_N_FP [
+ VBRSRQ_M_N_F
+ ])
+
+(define_int_iterator MVE_VBRSR_N_FP [
+ VBRSRQ_N_F
+ ])
+
;; MVE comparison iterators
(define_int_iterator MVE_CMP_M [
VCMPCSQ_M_U
@@ -900,6 +908,8 @@ (define_int_attr mve_insn [
(VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic")
(VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F "vbic")
(VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
+ (VBRSRQ_M_N_S "vbrsr") (VBRSRQ_M_N_U "vbrsr") (VBRSRQ_M_N_F
"vbrsr")
+ (VBRSRQ_N_S "vbrsr") (VBRSRQ_N_U "vbrsr") (VBRSRQ_N_F "vbrsr")
(VCLSQ_M_S "vcls")
(VCLSQ_S "vcls")
(VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 7898361b859..beca74d4964 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -529,15 +529,15 @@ (define_insn "mve_vpnotv16bi"
;;
;; [vbrsrq_n_f])
;;
-(define_insn "mve_vbrsrq_n_f<mode>"
+(define_insn "@mve_<mve_insn>q_n_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:SI 2 "s_register_operand" "r")]
- VBRSRQ_N_F))
+ MVE_VBRSR_N_FP))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vbrsr.<V_sz_elem> %q0, %q1, %2"
+ "<mve_insn>.<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -826,7 +826,7 @@ (define_expand "mve_vbicq_s<mode>"
;;
;; [vbrsrq_n_u, vbrsrq_n_s])
;;
-(define_insn "mve_vbrsrq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
@@ -834,7 +834,7 @@ (define_insn "mve_vbrsrq_n_<supf><mode>"
VBRSRQ_N))
]
"TARGET_HAVE_MVE"
- "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
+ "<mve_insn>.%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -2802,7 +2802,7 @@ (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
;;
;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
;;
-(define_insn "mve_vbrsrq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2812,7 +2812,7 @@ (define_insn "mve_vbrsrq_m_n_<supf><mode>"
VBRSRQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
+ "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3257,17 +3257,17 @@ (define_insn "@mve_<mve_insn>q_m_f<mode>"
;;
;; [vbrsrq_m_n_f])
;;
-(define_insn "mve_vbrsrq_m_n_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_n_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:SI 3 "s_register_operand" "r")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VBRSRQ_M_N_F))
+ MVE_VBRSR_M_N_FP))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
+ "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
--
2.34.1
