[Committed 09/11] RISC-V: Weaken mem_thread_fence

[Patrick O'Neill]

On 4/28/23 11:00, Jeff Law wrote:

On 4/27/23 10:22, Patrick O'Neill wrote:

This change brings atomic fences in line with table A.6 of the ISA
manual.

Relax mem_thread_fence according to the memmodel given.

2023-04-27 Patrick O'Neill <patr...@rivosinc.com>

gcc/ChangeLog:

    * config/riscv/sync.md (mem_thread_fence_1): Change fence
    depending on the given memory model.

OK
jeff

Committed.

Patrick