[PATCH v5 05/11] RISC-V: Add AMO release bits

[Patrick O'Neill]

This patch sets the relevant .rl bits on amo operations.

2023-04-27 Patrick O'Neill <patr...@rivosinc.com>

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_print_operand): change behavior
        of %A to include release bits.

Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02eb5125ac1..d46781d8981 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4503,8 +4503,13 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       break;
 
     case 'A':
-      if (riscv_memmodel_needs_amo_acquire (model))
+      if (riscv_memmodel_needs_amo_acquire (model)
+         && riscv_memmodel_needs_release_fence (model))
+       fputs (".aqrl", file);
+      else if (riscv_memmodel_needs_amo_acquire (model))
        fputs (".aq", file);
+      else if (riscv_memmodel_needs_release_fence (model))
+       fputs (".rl", file);
       break;
 
     case 'F':
-- 
2.34.1