Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA

[Jeff Law via Gcc-patches]

On 3/13/23 03:05, juzhe.zh...@rivai.ai wrote:

From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>

According to RVV ISA:
14. Vector Reduction Operations

"The destination vector register can overlap the source operands, including the mask 
register."

gcc/ChangeLog:

         * config/riscv/vector.md: Refine RA constraint.

OK.  Go ahead and install this on the trunk.

jeff