On 3/13/23 03:05, juzhe.zh...@rivai.ai wrote:
From: Ju-Zhe Zhong <juzhe.zh...@rivai.ai>
According to RVV ISA:
14. Vector Reduction Operations
"The destination vector register can overlap the source operands, including the mask
register."
gcc/ChangeLog:
* config/riscv/vector.md: Refine RA constraint.
This feels like it ought to wait for gcc-14 as well.
One question though, why even bother with the matching constraint at all
in these patterns? ISTM it doesn't really accomplish anything.
Removing it allows a single alternative to handle all the possibilities.
Jeff
