LoongArch 32-bit instruction set does not support crc* and crcc* instructions.
gcc/ChangeLog: * config/loongarch/larchintrin.h (__crc_w_b_w): Add macros for control. (__crc_w_h_w): Likewise. (__crc_w_w_w): Likewise. (__crcc_w_b_w): Likewise. (__crcc_w_h_w): Likewise. (__crcc_w_w_w): Likewise. * config/loongarch/loongarch.md: Add condition TARGET_64BIT to loongarch_crc_* loongarch_crcc_* instruction template. --- gcc/config/loongarch/larchintrin.h | 4 +--- gcc/config/loongarch/loongarch.md | 4 ++-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/gcc/config/loongarch/larchintrin.h b/gcc/config/loongarch/larchintrin.h index e571ed27b37..09f9a5db846 100644 --- a/gcc/config/loongarch/larchintrin.h +++ b/gcc/config/loongarch/larchintrin.h @@ -145,6 +145,7 @@ __asrtgt_d (long int _1, long int _2) #error "Unsupported ABI." #endif +#ifdef __loongarch64 /* Assembly instruction format: rd, rj, rk. */ /* Data types in instruction templates: SI, QI, SI. */ extern __inline int @@ -172,7 +173,6 @@ __crc_w_w_w (int _1, int _2) return (int) __builtin_loongarch_crc_w_w_w ((int) _1, (int) _2); } -#ifdef __loongarch64 /* Assembly instruction format: rd, rj, rk. */ /* Data types in instruction templates: SI, DI, SI. */ extern __inline int @@ -181,7 +181,6 @@ __crc_w_d_w (long int _1, int _2) { return (int) __builtin_loongarch_crc_w_d_w ((long int) _1, (int) _2); } -#endif /* Assembly instruction format: rd, rj, rk. */ /* Data types in instruction templates: SI, QI, SI. */ @@ -210,7 +209,6 @@ __crcc_w_w_w (int _1, int _2) return (int) __builtin_loongarch_crcc_w_w_w ((int) _1, (int) _2); } -#ifdef __loongarch64 /* Assembly instruction format: rd, rj, rk. */ /* Data types in instruction templates: SI, DI, SI. */ extern __inline int diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 3509c3c21c1..227f3c6899c 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -3539,7 +3539,7 @@ (define_insn "loongarch_crc_w_<size>_w" (unspec:SI [(match_operand:QHSD 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")] UNSPEC_CRC))] - "" + "TARGET_64BIT" "crc.w.<size>.w\t%0,%1,%2" [(set_attr "type" "unknown") (set_attr "mode" "<MODE>")]) @@ -3549,7 +3549,7 @@ (define_insn "loongarch_crcc_w_<size>_w" (unspec:SI [(match_operand:QHSD 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r")] UNSPEC_CRCC))] - "" + "TARGET_64BIT" "crcc.w.<size>.w\t%0,%1,%2" [(set_attr "type" "unknown") (set_attr "mode" "<MODE>")]) -- 2.31.1