>> Most likely than not you end up loading a larger quantity with the high >> bits zero'd. Interesting that we're using a packed model. I'd been >> told it was fairly expensive to implement in hardware relative to teh >> cost of implementing the sparse model.
>> I'm a bit confused by this. GCC can support single bit bools, though >> ports often extend them to 8 bits or more for computational efficiency >> purposes. At least that's the case in general. Is there something >> particularly special about masks & bools that's causing problems? I am not sure I am on the same page with you. I don't understand what is the sparse model you said. The only thing I do in this patch is that we change the BYTESIZE VNx1BI for example as the BYTESIZE of VNx1BI (Original I adjust all mask modes same size as VNx8QImode like LLVM). And I print the GET_MODE_SIZE (VNx1BI) the value is the same as VNx1QImode so I assume because GCC model 1-bool same as 1-QI??? Actually I not sure but I am sure after this patch, VNx1BI is adjusted smaller size. Adjusting mask modes as smaller size always beneficial, since we can use vlm && vsm in register spilling, it can reduce the memory consuming and load store hardware bandwidth. Unlike LLVM, LLVM make each fractional vector and mask vector same size as LMUL =1 so they use vl1r/vs1r to do the register spilling which is not optimal. juzhe.zh...@rivai.ai From: Jeff Law Date: 2022-12-17 09:53 To: 钟居哲; gcc-patches CC: kito.cheng; palmer Subject: Re: [PATCH] RISC-V: Fix RVV mask mode size On 12/16/22 18:44, 钟居哲 wrote: > Yes, VNx4DF only has 4 bit in mask mode in case of load and store. > For example vlm or vsm we will load store 8-bit ??? (I am not sure > hardward can load store 4bit,but I am sure it definetly not load store > the whole register size) Most likely than not you end up loading a larger quantity with the high bits zero'd. Interesting that we're using a packed model. I'd been told it was fairly expensive to implement in hardware relative to teh cost of implementing the sparse model. > So ideally it should be model more accurate. However, since GCC assumes > that 1 BOOL is 1-byte, the only thing I do is to model mask mode as > smallest as possible. > Maybe in the future, I can support 1BOOL for 1-bit?? I am not sure since > it will need to change GCC framework. I'm a bit confused by this. GCC can support single bit bools, though ports often extend them to 8 bits or more for computational efficiency purposes. At least that's the case in general. Is there something particularly special about masks & bools that's causing problems? Jeff
