LGTM. Thanks for fixing my mistake.
Let's see whether other RISC-V folks are happy with this patch.
juzhe.zh...@rivai.ai
From: jiawei
Date: 2022-11-15 16:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; jeffreyalaw; christoph.muellner;
philipp.tomsich; wuwei2016; jiawei
Subject: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.
Current epilogue will generate "addi sp,sp,0" redundant instruction.
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
addi sp,sp,0
ld s0,24(sp)
addi sp,sp,32
jr ra
```
Optimize it by check if adjust equal to zero, remove redundant insn gen.
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
ld s0,24(sp)
addi sp,sp,32
jr ra
```
Thanks for Kito and Jeff's suggestion, add testcase and fix code format.
jiawei (2):
RISC-V: Add spill sp adjust check testcase.
RISC-V: Optimize RVV epilogue logic.
gcc/config/riscv/riscv.cc | 35 ++++++++++---------
.../riscv/rvv/base/spill-sp-adjust.c | 13 +++++++
2 files changed, 32 insertions(+), 16 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
--
2.25.1
