[PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase.

[jiawei]

This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.

---
 .../gcc.target/riscv/rvv/base/spill-sp-adjust.c     | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
new file mode 100644
index 00000000000..0226554abf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)v; 
+}
+
+/* Make sure we do not have a useless SP adjustment.  */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */
-- 
2.25.1