On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt <pal...@rivosinc.com> wrote: > > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.toms...@vrull.eu wrote: > > > > This series provides support for the Ventana VT1 (a 4-way superscalar > > rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support > > for the supported instruction fusion patterns. > > > > This includes the addition of the fusion-aware scheduling > > infrastructure for RISC-V and implements idiom recognition for the > > fusion patterns supported by VT1. > > > > Note that we don't signal support for XVentanaCondOps at this point, > > as the XVentanaCondOps support is in-flight separately. Changing the > > defaults for VT1 can happen late in the cycle, so no need to link the > > two different changesets. > > > > Changes in v2: > > - Rebased and changed over to .rst-based documentation > > - Updated to catch more fusion cases > > - Signals support for Zifencei > > > > Philipp Tomsich (2): > > RISC-V: Add basic support for the Ventana-VT1 core > > RISC-V: Add instruction fusion (for ventana-vt1) > > > > gcc/config/riscv/riscv-cores.def | 3 + > > gcc/config/riscv/riscv-opts.h | 2 +- > > gcc/config/riscv/riscv.cc | 233 ++++++++++++++++++ > > .../risc-v-options.rst | 5 +- > > 4 files changed, 240 insertions(+), 3 deletions(-) > > I guess we never really properly talked about this on the GCC mailing > lists, but IMO it's fine to start taking code for designs that have been > announced under the assumption that if the hardware doesn't actually > show up according to those timelines that it will be assumed to have > never existed and thus be removed more quickly than usual. > > That said, I can't find anything describing that the VT-1 exists aside > from these patches. Is there anything that describes this design and > when it's expected to be available?
I have to defer to Jeff on this one. Philipp.
