On 11/13/22 13:48, Philipp Tomsich wrote:
The Ventana VT1 core supports quad-issue and instruction fusion.
This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences
together and adds idiom matcheing for the supported fusion cases.
gcc/ChangeLog:
* config/riscv/riscv.cc (enum riscv_fusion_pairs): Add symbolic
constants to identify supported fusion patterns.
(struct riscv_tune_param): Add fusible_op field.
(riscv_macro_fusion_p): Implement.
(riscv_fusion_enabled_p): Implement.
(riscv_macro_fusion_pair_p): Implement and recoginze fusible
idioms for Ventana VT1.
(TARGET_SCHED_MACRO_FUSION_P): Point to riscv_macro_fusion_p.
(TARGET_SCHED_MACRO_FUSION_PAIR_P): Point to riscv_macro_fusion_pair_p.
You know the fusion rules for VT1 better than I... I'm happy to largely
defer to you on this.
I do wonder if going forward hand matching RTL like this is going to be
an unmaintainable mess and whether or not we would be better served
using insn attributes to describe instruction fusion.
Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
---
Changes in v2:
- Update fusion patterns and catch some missing idioms/fusion pairs.
gcc/config/riscv/riscv.cc | 219 ++++++++++++++++++++++++++++++++++++++
1 file changed, 219 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 31d651f8744..43ba520885c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
+static bool
+riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
+{
+ rtx prev_set = single_set (prev);
+ rtx curr_set = single_set (curr);
+ /* prev and curr are simple SET insns i.e. no flag setting or branching. */
+ bool simple_sets_p = prev_set && curr_set && !any_condjump_p (curr);
+
+ if (!riscv_macro_fusion_p ())
+ return false;
+
+ if (simple_sets_p && (riscv_fusion_enabled_p (RISCV_FUSE_ZEXTW) ||
+ riscv_fusion_enabled_p (RISCV_FUSE_ZEXTH)))
Formatting nit. Bring the && down to a new line and if you still need a
line break for the "||", then the "||" should be on a new line as
well. Something like this...
if (simple_sets_p
&& (riscv_fusion_enabled_p (RISCV_FUSE_ZEXTW
|| riscv_fusion_enabled_p (RISCV_FUSE_ZEXTH)))
+ && REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO(SET_DEST (curr_set))
Space before open paren on this line.
+ && (( INTVAL (XEXP (SET_SRC (curr_set), 1)) == 32
+ && riscv_fusion_enabled_p(RISCV_FUSE_ZEXTW) )
+ || ( INTVAL (XEXP (SET_SRC (curr_set), 1)) < 32
+ && riscv_fusion_enabled_p(RISCV_FUSE_ZEXTWS))))
Extraneous spaces after the open parens before INTVALs above.
+ && REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO(SET_DEST (curr_set))
Missing whitespace before open paren on this line.
OK with the nits fixed.
Jeff
