Hi Maciej: I am convinced that is OK for now, I agree modeling fflags would be a rabbit hole, I tried to build a full GNU toolchain with my quick patch and saw many ICE during build libraries, that definitely should be a long-term optimization project.
Although I'm thinking if we should default -fno-trapping-math for RISC-V, because RISC-V didn't trap for any floating point operations, however I think that would be another topic. so you got my LGTM :) On Mon, Jul 18, 2022 at 11:43 PM Maciej W. Rozycki <ma...@embecosm.com> wrote: > > On Mon, 4 Jul 2022, Maciej W. Rozycki wrote: > > > These instructions are only produced via an expander already, so change > > the expander to emit individual RTL insns for each machine instruction > > in the ultimate ultimate sequence produced rather than deferring to a > > single RTL insn producing the whole sequence at once. > > Ping for: > > <https://gcc.gnu.org/pipermail/gcc-patches/2022-July/597767.html> > > Maciej
