RA now chooses GEN_OR_VSX_REGS in most cases. This is great in most
cases, but we often (or always?) use {l,st}{f,xs}iwzx now, which is
problematic because the integer load and store insns can use cheaper
addressing modes. We can fix that by putting a small penalty on the
instruction alternatives for those.
2022-04-21 Segher Boessenkool <seg...@kernel.crashing.org>
PR target/103197
PR target/102146
* config/rs6000/rs6000.md (zero_extendqi<mode>2 for EXTQI): Disparage
the "Z" alternatives in {l,st}{f,xs}iwzx.
(zero_extendhi<mode>2 for EXTHI): Ditto.
(zero_extendsi<mode>2 for EXTSI): Ditto.
(*movsi_internal1): Ditto.
(*mov<mode>_internal1 for QHI): Ditto.
(movsd_hardfloat): Ditto.
---
gcc/config/rs6000/rs6000.md | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index f05b8358ba0a..a39b95f7dffa 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -835,8 +835,8 @@ (define_mode_iterator ALTIVEC_DFORM [DF
;; complex forms. Basic data transfer is done later.
(define_insn "zero_extendqi<mode>2"
- [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand"
"m,r,Z,v")))]
+ [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,wa,^v")
+ (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand"
"m,r,?Z,v")))]
""
"@
lbz%U1%X1 %0,%1
@@ -889,8 +889,8 @@ (define_insn_and_split "*zero_extendqi<mode>2_dot2"
(define_insn "zero_extendhi<mode>2"
- [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand"
"m,r,Z,v")))]
+ [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,wa,^v")
+ (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand"
"m,r,?Z,v")))]
""
"@
lhz%U1%X1 %0,%1
@@ -944,7 +944,7 @@ (define_insn_and_split "*zero_extendhi<mode>2_dot2"
(define_insn "zero_extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
- (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand"
"m,r,Z,Z,r,wa,wa")))]
+ (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand"
"m,r,?Z,?Z,r,wa,wa")))]
""
"@
lwz%U1%X1 %0,%1
@@ -7496,7 +7496,7 @@ (define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r,
r, d, v,
- m, Z, Z,
+ m, ?Z, ?Z,
r, r, r, r,
wa, wa, wa, v,
wa, v, v,
@@ -7504,7 +7504,7 @@ (define_insn "*movsi_internal1"
r, *h, *h")
(match_operand:SI 1 "input_operand"
"r, U,
- m, Z, Z,
+ m, ?Z, ?Z,
r, d, v,
I, L, eI, n,
wa, O, wM, wB,
@@ -7785,11 +7785,11 @@ (define_expand "mov<mode>"
;; MTVSRWZ MF%1 MT%1 NOP
(define_insn "*mov<mode>_internal"
[(set (match_operand:QHI 0 "nonimmediate_operand"
- "=r, r, wa, m, Z, r,
+ "=r, r, wa, m, ?Z, r,
wa, wa, wa, v, ?v, r,
wa, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
- "r, m, Z, r, wa, i,
+ "r, m, ?Z, r, wa, i,
wa, O, wM, wB, wS, wa,
r, *h, r, 0"))]
"gpc_reg_operand (operands[0], <MODE>mode)
@@ -7973,10 +7973,10 @@ (define_insn "movsf_hardfloat"
;; FMR MR MT%0 MF%1 NOP
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
- "=!r, d, m, Z, ?d, ?r,
+ "=!r, d, m, ?Z, ?d, ?r,
f, !r, *c*l, !r, *h")
(match_operand:SD 1 "input_operand"
- "m, Z, r, wx, r, d,
+ "m, ?Z, r, wx, r, d,
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
--
1.8.3.1
