> -----Original Message-----
> From: Gcc-patches <gcc-patches-
> bounces+kyrylo.tkachov=arm....@gcc.gnu.org> On Behalf Of Christophe
> Lyon via Gcc-patches
> Sent: Thursday, January 13, 2022 2:56 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH v3 04/15] arm: Add GENERAL_AND_VPR_REGS regclass
>
> At some point during the development of this patch series, it appeared
> that in some cases the register allocator wants “VPR or general”
> rather than “VPR or general or FP” (which is the same thing as
> ALL_REGS). The series does not seem to require this anymore, but it
> seems to be a good thing to do anyway, to give the register allocator
> more freedom.
>
> CLASS_MAX_NREGS and arm_hard_regno_nregs need adjustment to avoid a
> regression in gcc.dg/stack-usage-1.c when compiled with -mthumb
> -mfloat-abi=hard -march=armv8.1-m.main+mve.fp+fp.dp.
Given the discussions I've seen on this patch (thanks Andre and Richard) this
is ok.
Though please rebase this as we've since renamed arm.c to arm.cc
Thanks,
Kyrill
>
> 2022-01-13 Christophe Lyon <christophe.l...@foss.st.com>
>
> gcc/
> * config/arm/arm.h (reg_class): Add GENERAL_AND_VPR_REGS.
> (REG_CLASS_NAMES): Likewise.
> (REG_CLASS_CONTENTS): Likewise.
> (CLASS_MAX_NREGS): Handle VPR.
> * config/arm/arm.c (arm_hard_regno_nregs): Handle VPR.
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index bb75921f32d..c3559ca8703 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -25287,6 +25287,9 @@ thumb2_asm_output_opcode (FILE * stream)
> static unsigned int
> arm_hard_regno_nregs (unsigned int regno, machine_mode mode)
> {
> + if (IS_VPR_REGNUM (regno))
> + return CEIL (GET_MODE_SIZE (mode), 2);
> +
> if (TARGET_32BIT
> && regno > PC_REGNUM
> && regno != FRAME_POINTER_REGNUM
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index dacce2b7f08..2416fb5ef64 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -1287,6 +1287,7 @@ enum reg_class
> SFP_REG,
> AFP_REG,
> VPR_REG,
> + GENERAL_AND_VPR_REGS,
> ALL_REGS,
> LIM_REG_CLASSES
> };
> @@ -1316,6 +1317,7 @@ enum reg_class
> "SFP_REG", \
> "AFP_REG", \
> "VPR_REG", \
> + "GENERAL_AND_VPR_REGS", \
> "ALL_REGS" \
> }
>
> @@ -1344,6 +1346,7 @@ enum reg_class
> { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */
> \
> { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */
> \
> { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */
> \
> + { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /*
> GENERAL_AND_VPR_REGS. */ \
> { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */
> \
> }
>
> @@ -1453,7 +1456,9 @@ extern const char
> *fp_sysreg_names[NB_FP_SYSREGS];
> ARM regs are UNITS_PER_WORD bits.
> FIXME: Is this true for iWMMX? */
> #define CLASS_MAX_NREGS(CLASS, MODE) \
> - (ARM_NUM_REGS (MODE))
> + (CLASS == VPR_REG) \
> + ? CEIL (GET_MODE_SIZE (MODE), 2) \
> + : (ARM_NUM_REGS (MODE))
>
> /* If defined, gives a class of registers that cannot be used as the
> operand of a SUBREG that changes the mode of the object illegally. */
> --
> 2.25.1
