[PATCH v3 15/15] arm: Fix constraint check for V8HI in mve_vector_mem_operand

[Christophe Lyon via Gcc-patches]

When compiling gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c with
-mthumb -mfloat-abi=hard -march=armv8.1-m.main+mve.fp+fp.dp, the compiler
crashes because:
error: insn does not satisfy its constraints:
(insn 28 14 17 2 (set (reg:V8HI 16 s0 [orig:249 u16 ] [249])
    (mem/c:V8HI (pre_modify:SI (reg/f:SI 12 ip [248])
            (plus:SI (reg/f:SI 12 ip [248])
                (const_int 32 [0x20]))) [1 u16+0 S16 A64])) 
"arm_mve.h":17113:10 3011 {*mve_movv8hi}
    (expr_list:REG_INC (reg/f:SI 12 ip [248])
      (nil)))
during RTL pass: reload

We are trying to generate:
vldrh.16        q3, [ip], #14
but the constraint check fails because ip is not a low reg.

This patch replaces LAST_LO_REGNUM by LAST_ARM_REGNUM in
mve_vector_mem_operand and avoids the ICE.

2022-01-13  Christophe Lyon  <christophe.l...@foss.st.com>

        gcc/
        * config/arm/arm.c (mve_vector_mem_operand): Fix handling of V8HI.

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7d56fa71806..5edca248fb7 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -13479,7 +13479,7 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool 
strict)
          case E_V4HImode:
          case E_V4HFmode:
            if (val % 2 == 0 && abs (val) <= 254)
-             return reg_no <= LAST_LO_REGNUM
+             return reg_no <= LAST_ARM_REGNUM
                || reg_no >= FIRST_PSEUDO_REGISTER;
            return FALSE;
          case E_V4SImode:
-- 
2.25.1