On Wed, Nov 24, 2021 at 9:06 AM Kong, Lingling <lingling.k...@intel.com> wrote: > > Hi Uros, > > > BTW: When playing with my patch, I introduced (define_insn > > "*vec_set<mode>_0" ...) to optimize scalar load to a vector. Does > > ix86_expand_vector_set work OK without this pattern? > > Yes, ix86_expand_vector_set could work ok with (define_insn > "<sse2p4_1>_pinsr<ssemodesuffix>"), this insn can optimize scalar load to a > vector.
Ah, now I remember - this pattern can be used to optimize HI/HF mode scalar loads in the same way as other "vec_set<mode>_0" patterns are used. It is similar to e.g. VI4F_128 mode vec_set<mode>_0 pattern. I was not able to test it properly without AVX512FP16, but the pattern is otherwise independent of the proposed patch. Uros.
