> -----Original Message-----
> From: Tamar Christina <tamar.christ...@arm.com>
> Sent: Wednesday, September 29, 2021 5:20 PM
> To: gcc-patches@gcc.gnu.org
> Cc: nd <n...@arm.com>; Richard Earnshaw <richard.earns...@arm.com>;
> Marcus Shawcroft <marcus.shawcr...@arm.com>; Kyrylo Tkachov
> <kyrylo.tkac...@arm.com>; Richard Sandiford
> <richard.sandif...@arm.com>
> Subject: [PATCH 4/7]AArch64 Add pattern xtn+xtn2 to uzp2
>
> Hi All,
>
> This turns truncate operations with a hi/lo pair into a single permute of half
> the bit size of the input and just ignoring the top bits (which are truncated
> out).
>
> i.e.
>
> void d2 (short * restrict a, int *b, int n)
> {
> for (int i = 0; i < n; i++)
> a[i] = b[i];
> }
>
> now generates:
>
> .L4:
> ldp q0, q1, [x3]
> add x3, x3, 32
> uzp1 v0.8h, v0.8h, v1.8h
> str q0, [x5], 16
> cmp x4, x3
> bne .L4
>
> instead of
>
> .L4:
> ldp q0, q1, [x3]
> add x3, x3, 32
> xtn v0.4h, v0.4s
> xtn2 v0.8h, v1.4s
> str q0, [x5], 16
> cmp x4, x3
> bne .L4
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>
> Ok for master?
>
Ok.
Thanks,
Kyrill
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd.md
> (*aarch64_narrow_trunc<mode>): New.
> * config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd):
> New.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/aarch64/xtn-combine-1.c: New test.
> * gcc.target/aarch64/narrow_high_combine.c: Update case.
>
> --- inline copy of patch --
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index
> 36396ef236e8c476d5e2f1acee80dc54ec5ebe4e..33e3301d229366022a5b9481
> b6c3ae8f8d93f9e2 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -1753,6 +1753,18 @@ (define_expand "aarch64_xtn2<mode>"
> }
> )
>
> +(define_insn "*aarch64_narrow_trunc<mode>"
> + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
> + (vec_concat:<VNARROWQ2>
> + (truncate:<VNARROWQ>
> + (match_operand:VQN 1 "register_operand" "w"))
> + (truncate:<VNARROWQ>
> + (match_operand:VQN 2 "register_operand" "w"))))]
> + "TARGET_SIMD"
> + "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"
> + [(set_attr "type" "neon_permute<q>")]
> +)
> +
> ;; Packing doubles.
>
> (define_expand "vec_pack_trunc_<mode>"
> diff --git a/gcc/config/aarch64/iterators.md
> b/gcc/config/aarch64/iterators.md
> index
> 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd072
> 62a9471ab13d5488e 100644
> --- a/gcc/config/aarch64/iterators.md
> +++ b/gcc/config/aarch64/iterators.md
> @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI
> V4SI])
> ;; Advanced SIMD modes for H, S and D types.
> (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
>
> +;; Modes for which we can narrow the element and increase the lane counts
> +;; to preserve the same register size.
> +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI
> "V8HI")
> + (V2SI "V4HI") (V2DI "V4SI")])
> +
> +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi")
> + (V2SI "v4hi") (V2DI "v4si")])
> +
> ;; Advanced SIMD and scalar integer modes for H and S.
> (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> index
> 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e
> 12b15dfeab8c7e71 100644
> --- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
> @@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t,
> s64, u32)
> /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */
> -/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */
> +/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */
> +/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */
> /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
> b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
> new file mode 100644
> index
> 0000000000000000000000000000000000000000..ed655cc970a602da4ace78d
> c8dbd64ab18b0d4ab
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do assemble } */
> +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
> +
> +void d2 (short * restrict a, int *b, int n)
> +{
> + for (int i = 0; i < n; i++)
> + a[i] = b[i];
> +}
> +
> +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
> +/* { dg-final { scan-assembler-not {\txtn\t} } } */
> +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
>
>
> --
