2021-09-23 Kito Cheng <[email protected]>
gcc/ChangeLog:
* common/config/riscv/riscv-common.c (riscv_ext_version_table):
Add zba, zbb, zbc and zbs.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZBA): New.
(MASK_ZBB): Ditto.
(MASK_ZBC): Ditto.
(MASK_ZBS): Ditto.
(TARGET_ZBA): Ditto.
(TARGET_ZBB): Ditto.
(TARGET_ZBC): Ditto.
(TARGET_ZBS): Ditto.
* config/riscv/riscv.opt (riscv_zb_subext): New.
---
gcc/common/config/riscv/riscv-common.c | 10 ++++++++++
gcc/config/riscv/riscv-opts.h | 10 ++++++++++
gcc/config/riscv/riscv.opt | 3 +++
3 files changed, 23 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.c
b/gcc/common/config/riscv/riscv-common.c
index 10868fd417d..37b6ea80086 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -101,6 +101,11 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
+ {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
+
/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
};
@@ -906,6 +911,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[]
=
{"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
{"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
+ {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA},
+ {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB},
+ {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC},
+ {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f4cf6ca4b82..2efc4b80f1f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -73,4 +73,14 @@ enum stack_protector_guard {
#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
+#define MASK_ZBA (1 << 0)
+#define MASK_ZBB (1 << 1)
+#define MASK_ZBC (1 << 2)
+#define MASK_ZBS (1 << 3)
+
+#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
+#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
+#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
+#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
+
#endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 5ff85c21430..15bf89e17c2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
+TargetVariable
+int riscv_zb_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
--
2.33.0
