On Wed, Aug 11, 2021 at 7:16 PM Uros Bizjak <ubiz...@gmail.com> wrote:
>
> On Wed, Aug 11, 2021 at 8:36 AM Uros Bizjak <ubiz...@gmail.com> wrote:
> >
> > On Tue, Aug 10, 2021 at 2:13 PM liuhongt <hongtao....@intel.com> wrote:
> > >
> > > Hi:
> > > AVX512F supported vscalefs{s,d} which is the same as ldexp except the
> > > second operand should be floating point.
> > > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> > >
> > > gcc/ChangeLog:
> > >
> > > PR target/98309
> > > * config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd]
> > > when TARGET_AVX512F and TARGET_SSE_MATH.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > PR target/98309
> > > * gcc.target/i386/pr98309-1.c: New test.
> > > * gcc.target/i386/pr98309-2.c: New test.
> >
> > OK.
>
> Actually, we should introduce a scalar version of avx512f_vmscalef, so
> we can avoid all subreg conversions with the vector-merge (VM)
> version, and will also allow memory in operand 2.
>
> Please test the attached incremental patch.
>
Bootstrapped and regtested on x86_64-linux-gnu{-m32,} on CLX.
tests is fine.
> Uros.
--
BR,
Hongtao
