Re: [PATCH] aarch64: Use correct type attributes for RTL generating XTN(2)

[Richard Sandiford via Gcc-patches]

Jonathan Wright <jonathan.wri...@arm.com> writes:
> Hi,
>
> As subject, this patch corrects the type attribute in RTL patterns that
> generate XTN/XTN2 instructions to be "neon_move_narrow_q".
>
> This makes a material difference because these instructions can be
> executed on both SIMD pipes in the Cortex-A57 core model, whereas the
> "neon_shift_imm_narrow_q" attribute (in use until now) would suggest
> to the scheduler that they could only execute on one of the two
> pipes.
>
> Regression tested and bootstrapped on aarch64-none-linux-gnu - no
> issues.
>
> Ok for master?

OK, thanks.

Richard

> Thanks,
> Jonathan
>
> ---
>
> gcc/ChangeLog:
>
> 2021-05-18  Jonathan Wright  <jonathan.wri...@arm.com>
>
>         * config/aarch64/aarch64-simd.md: Use "neon_move_narrow_q"
>         type attribute in patterns generating XTN(2).
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md 
> b/gcc/config/aarch64/aarch64-simd.md
> index 
> 447b5575f2f5adbad4957e90787a4954af644b20..e750faed1dbd940cdfa216d858b98f3bc25bba42
>  100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -1697,7 +1697,7 @@
>       (truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w")))]
>    "TARGET_SIMD"
>    "xtn\\t%0.<Vntype>, %1.<Vtype>"
> -  [(set_attr "type" "neon_shift_imm_narrow_q")]
> +  [(set_attr "type" "neon_move_narrow_q")]
>  )
>  
>  (define_insn "aarch64_xtn2<mode>_le"
> @@ -1707,7 +1707,7 @@
>         (truncate:<VNARROWQ> (match_operand:VQN 2 "register_operand" "w"))))]
>    "TARGET_SIMD && !BYTES_BIG_ENDIAN"
>    "xtn2\t%0.<V2ntype>, %2.<Vtype>"
> -  [(set_attr "type" "neon_shift_imm_narrow_q")]
> +  [(set_attr "type" "neon_move_narrow_q")]
>  )
>  
>  (define_insn "aarch64_xtn2<mode>_be"
> @@ -1717,7 +1717,7 @@
>         (match_operand:<VNARROWQ> 1 "register_operand" "0")))]
>    "TARGET_SIMD && BYTES_BIG_ENDIAN"
>    "xtn2\t%0.<V2ntype>, %2.<Vtype>"
> -  [(set_attr "type" "neon_shift_imm_narrow_q")]
> +  [(set_attr "type" "neon_move_narrow_q")]
>  )
>  
>  (define_expand "aarch64_xtn2<mode>"
> @@ -8618,7 +8618,7 @@
>       (truncate:<VNARROWQ> (match_operand:VQN 1 "register_operand" "w")))]
>    "TARGET_SIMD"
>    "xtn\t%0.<Vntype>, %1.<Vtype>"
> -  [(set_attr "type" "neon_shift_imm_narrow_q")]
> +  [(set_attr "type" "neon_move_narrow_q")]
>  )
>  
>  (define_insn "aarch64_bfdot<mode>"