On Mon, Apr 26, 2021 at 5:45 AM Christoph Muellner <cmuell...@gcc.gnu.org> wrote:
> This series provides a cleanup of the current atomics implementation > of RISC-V: > This looks OK to me, other than the issue with address instructions emitted inside the lr/sc loop. That could be fixed with a follow up patch though. amoswap is probably faster than a fence followed by a store, but they aren't exactly the same operation, since I think the amoswap only provides consistency for the target address whereas the fence would provide consistency for all addresses. It does look odd that we were using amoswap here. The inconsistency with atomic_load might be a problem. I'm OK with dropping this. I'm not sure if we are implementing the __sync_* builtins properly. Most of them are defined as full barriers. With our weak memory model RVWMO, that implies that we need a fence along with an amo instruction. However, this is broken without your patch, and not made any worse by your patch, so it isn't an issue with your patch. Just a FYI. See for instance the discussion in PR 65697 and the patch to fix this for aarch64. https://gcc.gnu.org/git/?p=gcc.git;a=blobdiff;f=gcc/config/aarch64/aarch64.c;h=93bea074d6831b2aea2c0a40dacddc9ad20788c7;hp=648a548e0e06d2968fb74e4b588c368db060ad74;hb=f70fb3b635f9618c6d2ee3848ba836914f7951c2;hpb=fc65eccabc6d6e881ff5efcd674aa3791cf8cee6 Jim
