Hi, As subject, this patch implements the saturating right-shift and narrow high Neon intrinsic RTL patterns using a vec_concat of a register_operand and a VQSHRN_N unspec - instead of just a VQSHRN2_N unspec. This more relaxed pattern allows for more aggressive combinations and ultimately better code generation.
Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.
Ok for master?
Thanks,
Jonathan
---
gcc/ChangeLog:
2021-03-04 Jonathan Wright <jonathan.wri...@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n2_n<mode>):
Implement as an expand emitting a big/little endian
instruction pattern.
(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_le): Define.
(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_be): Define.
* config/aarch64/iterators.md: Add VQSHRN2_N iterator and
constituent unspecs.
rb14251.patch
Description: rb14251.patch
