[PATCH 16/20] aarch64: Relax aarch64_hn2 RTL pattern

[Jonathan Wright via Gcc-patches]

Hi,

As subject, this patch implements the v[r]addhn2 and v[r]subhn2 Neon
intrinsic RTL patterns using a vec_concat of a register_operand and an
ADDSUBHN unspec - instead of just an ADDSUBHN2 unspec. This more
relaxed pattern allows for more aggressive combinations and ultimately
better code generation.

Regression tested and bootstrapped on aarch64-none-linux-gnu and
aarch64_be-none-elf - no issues.

Ok for master?

Thanks,
Jonathan

---

gcc/ChangeLog:

2021-03-03  Jonathan Wright  <jonathan.wri...@arm.com>

        * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>):
        Implement as an expand emitting a big/little endian
        instruction pattern.
        (aarch64_<sur><addsub>hn2<mode>_insn_le): Define.
        (aarch64_<sur><addsub>hn2<mode>_insn_be): Define.

rb14250.patch
Description: rb14250.patch